View HI-6130_7550540.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

holt integrated circuits www.holtic.com 1 HI-6130 / hi-6131 / hi-6132 mil-std-1553 / mil-std-1760 3.3v bc / mt / rt multi-terminal device general descpiption the 3.3v cmos hi-613x device provides a complete single- or multi-function interface between a host processor and mil-std-1553b bus. each ic contains a bus controller (bc), a bus monitor terminal (mt) and two independent remote terminals (rts). any combination of the contained 1553 functions can be enabled for concurrent operation. the enabled terminals communicate with the mil-std-1553 buses through a shared on-chip dual bus transceiver and external transformer. the user allocates 64k bytes of on-chip static ram between devices to suit application requirements. two options are offered for host access to internal registers and static ram: the HI-6130 uses a 16-bit parallel bus; the hi-6131 communicates with the host via a 4-wire serial peripheral interface (spi). the hi- 6132 combines both 16-bit parallel bus and spi in a single 15 x 15mm hermetically sealed ceramic package. device host interface packages HI-6130 16-bit parallel 100-pin pqfp hi-6131 4-wire spi 64-pin qfn 64-pin pqfp hi-6132 16-bit parallel or 4-wire spi 121 ceramic pga or lga programmable interrupts provide terminal status to the host processor. circular data buffers in ram have interrupts for rollover and programmable level attained. the hi-613x can be confgured for automatic self-initialization after reset. a dedicated spi port reads data from an external serial eeprom to fully confgure registers and ram for any subset of one to four terminal devices. features ? concurrent multi-terminal operation for one to four mil-std-1553b functions: bc, mt and two independent rts. ? 64k bytes internal static ram with ram error detection/correction option. ? autonomous terminal operation requires minimal host intervention. ? shared mil-std-1553 bus interface reduces circuit complexity and circuit board area. ? fully programmable bus controller with 28 op code instruction set. ? simple monitor terminal (smt) mode records commands and data separately, with 16-bit or 48- bit time tagging. ? irig monitor terminal (imt) mode supports irig- 106 chapter 10 packet format. ? imt monitor mode can optionally generate complete irig-106 data packets, including full packet headers and trailers. ? independent 16-bit time tag counters and clock sources for all terminals. the bus controller and monitor also have 32- and 48-bit time count options, respectively. ? 64-word interrupt log buffer queues the most recent 32 interrupts. hardware-assisted interrupt decoding quickly identifes interrupt sources. ? built-in self-test for protocol logic, digital signal paths and internal ram. ? optional self-initialization at reset uses external serial eeprom. ? 8kv esd protection (hbm, all pins). ? two temperature ranges: -40 o c to +85 o c, or -55 o c to +125 o c with optional burn-in. ? rohs compliant. pin configuration (top) top view a3 - 27 rt1ena - 26 a4 - 28 a5 - 29 rt2a_4 - 50 rt2ap - 49 a6 - 33 rt1ap - 30 miso - 31 mosi - 32 a7 - 34 a8 - 35 a9 - 43 vcc - 36 gnd - 37 eecopy - 41 ttclk - 38 mttclk - 39 esck - 42 a10 - 44 a11 - 45 mtrun - 46 rt2ssf - 47 rt2lock - 48 ecs - 40 100 - d11 99 - d10 78 - vcc 77 - gnd 76 - d2 98 - d9 97 - txinhb 96 - txinha 95 - autoen 94 - d8 93 - d7 92 - d6 91 - vcc 90 - gnd 89 - d5 88 - d4 87 - d3 86 - rt1ssf 85 - active 84 - ready 83 - mtpkrdy 80 - ackirq vcc - 1 gnd - 2 d12 - 4 d14 - 6 d15 - 7 ramedc - 8 bctrig - 3 mode - 10 mclk - 13 gnd - 14 wait / wait - 15 rt1a_0 - 17 rt1a_1 - 18 rt1a_2 - 19 rt1a_3 - 21 rt1a_4 - 22 a0 - 23 a1 - 24 a2 - 25 d13 - 5 vcc - 12 ce - 9 str / oe - 11 r/w / we - 16 mr - 20 75 - d1 74 - d0 71 - bendi 70 - test 69 - rt1lock 68 - mtstoff 67 - bcena 66 - busa 62 - vccp 65 - vccp 61 - busb 60 - rt2ena 52 - a12 59 - rt2a_0 58 - rt2a_1 57 - rt2a_2 56 - rt2a_3 73 - wpol 72 - btype 51 - a13 54 - a15 55 - bwid 53 - a14 63 - busb 64 - busa HI-6130pqxf 79 - irq 81 - rt1mc8 82 - rt2mc8 ds6130 rev. f 12/12 december, 2012
holt integrated circuits 2 notes: HI-6130, hi-6131
holt integrated circuits 3 table of contents 1. block diagram ........................................................................................... 14 2. feature overview ................................................................................... 15 2.1. bus controller operation .......................................................................................... 15 2.2. remote terminal operation ...................................................................................... 15 2.3. monitor terminal operation ....................................................................................... 15 2.4. interrupts ................................................................................................................... 15 2.5. reset and initialization .............................................................................................. 15 3. pin descriptions ....................................................................................... 16 4. memory map ................................................................................................. 21 5. ram structures ....................................................................................... 22 5.1. interrupt log data buffer .......................................................................................... 22 5.2. bus controller (bc) instruction list ........................................................................... 22 5.3. bus controller (bc) msg control / status stack ....................................................... 22 5.4. bus controller (bc) call stack .................................................................................. 22 5.5. bus controller (bc) general purpose queue ........................................................... 22 5.6. monitor terminal temporary buffers a & b ............................................................... 22 5.7. monitor terminal (mt) address list .......................................................................... 22 5.8. monitor terminal (mt) message filter table ............................................................. 22 5.9. monitor terminal (mt) data buffers .......................................................................... 22 5.10. rt1 and rt2 command illegalization tables ........................................................... 22 5.11. rt1 and rt2 descriptor tables ................................................................................ 23 5.12. rt1 and rt2 temporary receive buffers ................................................................ 23 5.13. rt message data buffers ......................................................................................... 23 5.14. rt storage for mode code commands .................................................................... 23 6. hardware features ................................................................................ 23 6.1. remote terminal address inputs .............................................................................. 23 6.2. dual transceivers for mil-std-1553 bus ................................................................ 23 6.3. encoder and decoders ............................................................................................. 23 6.4. auto-initialization serial eeprom interface ............................................................. 23 6.5. selection of host interface (hi-6132 only) ................................................................ 24 HI-6130, hi-6131
holt integrated circuits 4 7. register & memory addressing .......................................................... 24 7.1. 8-bit bus operation: (HI-6130 only) ......................................................................... 24 8. register definitions ............................................................................... 24 9. registers used by all device functions ........................................ 29 9.1. master configuration register (0x0000) ................................................................... 29 9.2. master status and reset register (0x0001) ............................................................ 33 9.3. overview of interrupts ............................................................................................... 36 9.4. hardware interrupt behavior ..................................................................................... 36 9.5. interrupt count & log address register (0x000a) ................................................... 37 9.6. interrupt log buffer ................................................................................................... 38 9.7. hardware interrupt registers .................................................................................... 40 9.7.1. hardware interrupt enable register (0x000f) ...................................................... 40 9.7.2. hardware pending interrupt register (0x0006) .................................................... 40 9.7.3. hardware interrupt output enable register (0x0013) .......................................... 40 9.8. time tag counter configuration ............................................................................... 44 9.9. time tag counter configuration register (0x0039) .................................................. 45 9.10. memory address pointer registers (hi-6131 only) ................................................... 49 10. bus controller ? configuration and operation ........................ 51 10.1. bus controller condition codes ................................................................................ 52 10.2. bus controller instruction op codes ........................................................................ 55 10.3. bus controller general purpose queue ................................................................... 63 10.4. bus controller message control / status blocks ...................................................... 63 10.4.1. bc control word ................................................................................................... 64 10.4.2. time to next message word ................................................................................. 68 10.4.3. data block pointer ................................................................................................. 68 10.4.4. bc block status word ........................................................................................... 69 11. bus controller register description .......................................... 73 11.1. bc (bus controller) configuration register (0x0032) ............................................... 73 11.2. start address register for bus controller (bc) instruction list (0x0033) ................. 82 11.3. bus controller (bc) instruction list pointer (0x0034) ............................................... 82 11.4. bus controller (bc) frame time remaining register (0x0035) ............................... 83 11.5. bus controller (bc) time to next message register (0x0036) ................................ 83 11.6. bus controller (bc) condition code register (read 0x0037) .................................. 83 HI-6130, hi-6131
holt integrated circuits 5 11.7. bus controller (bc) general purpose flag register (write 0x0037) ........................ 86 11.8. bus controller (bc) general purpose queue pointer register (0x0038) ................. 86 11.9. bus controller (bc) time tag counter (0x0043) ...................................................... 87 11.10. bus controller (bc) time tag counter high (0x0044) .............................................. 87 11.11. bus controller (bc) time tag utility register (0x0045) ........................................... 88 11.12. bus controller (bc) time tag utility high register (0x0046) .................................. 88 11.13. bus controller (bc) time tag match register (0x0047) .......................................... 88 11.14. bus controller (bc) time tag match high register (0x0048) ................................. 88 11.15. bus controller interrupt registers and their use ..................................................... 89 11.15.1. bus controller (bc) interrupt enable register (0x0010) ...................................... 90 11.15.2. bus controller (bc) pending interrupt register (0x0007) .................................... 90 11.15.3. bus controller (bc) interrupt output enable register (0x0014) .......................... 90 12. simple monitor terminal (smt) ............................................................ 93 12.1. overview ................................................................................................................... 93 12.2. smt block status word (bsw) description ............................................................. 98 12.3. smt message filter table ...................................................................................... 101 13. simple monitor terminal (smt) register description ............. 103 13.1. smt configuration register (0x0029) .................................................................... 103 13.2. smt bus monitor address list start address register (0x002f) ........................... 106 13.3. smt next message command buffer address (0x0030) ....................................... 106 13.4. smt last message command buffer address (0x0031) ........................................ 107 13.5. smt bus monitor time tag count register (0x003a) ............................................ 107 13.6. smt bus monitor time tag count mid register (0x003b) ..................................... 107 13.7. smt bus monitor time tag count high register (0x003c) .................................... 107 13.8. smt bus monitor time tag utility register (0x003d) ............................................. 108 13.9. smt bus monitor time tag utility mid register (0x003e) ...................................... 108 13.10. smt bus monitor time tag utility high register (0x003f) ..................................... 108 13.11. smt bus monitor time tag match register (0x0040) ............................................ 109 13.12. smt bus monitor time tag match mid register (0x0041) ..................................... 109 13.13. smt bus monitor time tag match high register (0x0042) ................................... 109 13.14. smt bus monitor interrupt registers and their use .............................................. 110 13.14.1. smt bus monitor interrupt enable register (0x0011) .......................................... 111 13.14.2. smt bus monitor pending interrupt register (0x0008) ........................................ 111 13.14.3. smt bus monitor interrupt output enable register (0x0015) .............................. 111 HI-6130, hi-6131
holt integrated circuits 6 14. irig-106 monitor terminal (imt) .......................................................... 113 14.1. overview ................................................................................................................. 113 14.2. irig-106 bus monitor - data packet format .......................................................... 114 14.3. irig-106 packet header description ...................................................................... 116 14.3.1. packet sync pattern. .......................................................................................... 116 14.3.2. channel id. ......................................................................................................... 116 14.3.3. packet length. .................................................................................................... 116 14.3.4. data length. ....................................................................................................... 116 14.3.5. data type version. ............................................................................................. 116 14.3.6. sequence number. ............................................................................................. 116 14.3.7. packet flags. ...................................................................................................... 116 14.3.8. data type. .......................................................................................................... 117 14.3.9. relative time counter. ....................................................................................... 117 14.3.10. header checksum. ............................................................................................. 117 14.4. irig-106 packet trailer description ....................................................................... 117 14.5. irig-106 data packet trailer description ............................................................... 117 14.5.1. channel specific data. ....................................................................................... 118 14.5.2. irig-106 intra-packet time stamp. ................................................................... 118 14.5.3. irig-106 intra-packet data header. .................................................................. 118 14.5.4. irig-106 message data. .................................................................................... 118 14.6. imt block status word (bsw) description ............................................................. 119 14.7. imt message filter table ........................................................................................ 122 15. irig-106 bus monitor (imt) configuration and operation ........ 125 15.1. generating complete irig-106 data packets ......................................................... 125 15.2. generating only irig-106 packet body (no header or trailer) ................................ 125 16. registers used by the imt bus monitor ........................................ 128 16.1. imt bus monitor mt configuration register (0x0029) ............................................ 128 16.2. imt bus monitor address list start address register (0x002f) ............................. 132 16.3. imt bus monitor next message storage pointer (0x0030) .................................... 132 16.4. imt bus monitor last message buffer address (0x0031) ....................................... 132 16.5. imt packet maximum message count register (0x002a) ..................................... 133 16.5.1. practical irig-106 packet message count considerations .................................. 133 16.6. imt packet maximum 1553 word count register (0x002b) .................................. 133 16.6.1. practical irig-106 packet word count considerations ......................................... 134 HI-6130, hi-6131
holt integrated circuits 7 16.7. imt maximum packet time register (0x002c) ...................................................... 134 16.7.1. practical irig-106 packet time considerations .................................................... 134 16.8. imt packet maximum gap time register (0x002d) .............................................. 134 16.8.1. practical irig-106 maximum gap time considerations ........................................ 135 16.9. imt packet header channel id register (0x002e) ................................................ 135 16.10. imt monitor time tag count low register (0x003a) ............................................. 136 16.11. imt monitor time tag count mid register (0x003b) .............................................. 136 16.12. imt monitor time tag count high register (0x003c) ............................................ 136 16.13. imt time tag utility low register (0x003d) ........................................................... 136 16.14. imt time tag utility mid register (0x003e) ............................................................ 137 16.15. imt time tag utility high register (0x003f) .......................................................... 137 16.15.1. loading a 48-bit value into the three 16-bit smt time tag count registers ..... 137 16.15.2. capturing a 48-bit value from the three 16-bit smt time tag count registers . 137 16.16. imt time tag match low register (0x0040) .......................................................... 137 16.17. imt time tag match mid register (0x0041) ........................................................... 137 16.18. imt time tag match high register (0x0042) .......................................................... 138 16.19. imt bus monitor interrupt registers and their use ................................................ 139 16.19.1. imt bus monitor interrupt enable register (0x0011) .......................................... 140 16.19.2. imt bus monitor pending interrupt register (0x0008) ........................................ 140 16.19.3. imt bus monitor interrupt output enable register (0x0015) .............................. 140 17. single or dual remote terminal(s) ? overview ......................... 143 18. registers used by remote terminals rt1 and rt2 .................... 144 18.1. remote terminal 1 (rt1) confguration register (0x0017) remote terminal 2 (rt2) confguration register (0x0020) .................................... 144 18.2. remote terminal 1 (rt1) operational status register (0x0018) remote terminal 2 (rt2) operational status register (0x0021) ........................... 148 18.3. remote terminal 1 (rt1) current command register (0x0002) remote terminal 2 (rt2) current command register (0x0004) ............................ 150 18.4. remote terminal 1 (rt1) current control word address register (0x0003) remote terminal 2 (rt2) current control word address register (0x0005) ......... 150 18.5. remote terminal 1 (rt1) descriptor table base address register (0x0019) remote terminal 2 (rt2) descriptor table base address register (0x0022) ........ 150 18.6. remote terminal 1 (rt1) mil-std-1553 status word bits register (0x001a) remote terminal 2 (rt2) mil-std-1553 status word bits register (0x0023) ...... 151 18.7. remote terminal 1 (rt1) current message information word register (0x001b) remote terminal 2 (rt2) current message information word register (0x0024) . 152 HI-6130, hi-6131
holt integrated circuits 8 18.8. remote terminal 1 (rt1) bus a select register (0x001c) remote terminal 2 (rt2) bus a select register (0x0025) ..................................... 153 18.9. remote terminal 1 (rt1) bus b select register (0x001d) remote terminal 2 (rt2) bus b select register (0x0026) ..................................... 153 18.10. remote terminal 1 (rt1) built-in test (bit) word register (0x001e) remote terminal 2 (rt2) built-in test (bit) word register (0x0027) .................... 154 18.11. remote terminal 1 (rt1) alternate built-in test (bit) word register (0x001f) remote terminal 2 (rt2) alternate built-in test (bit) word register (0x0028) ..... 155 18.12. remote terminal 1 (rt1) time tag counter register (0x0049) remote terminal 2 (rt2) time tag counter register (0x004b) ............................ 155 18.13. remote terminal 1 (rt1) time tag utility register (0x004a) remote terminal 2 (rt2) time tag utility register (0x004c) ................................ 156 18.13.1. rt time tag counter loading ............................................................................ 156 18.13.2. rt time tag count match interrupts .................................................................. 156 18.14. rt1 and rt2 remote terminal interrupt registers and their use ........................ 157 18.14.1. remote terminal (rt) interrupt enable register (0x0012) ................................. 158 18.14.2. remote terminal (rt) pending interrupt register (0x0009) ............................... 158 18.14.3. remote terminal (rt) interrupt output enable register (0x0016) ..................... 158 19. remote terminal rt1 and rt2 configuration and operation 161 19.1. command responses ............................................................................................ 161 19.1.1. rt to rt commands. ......................................................................................... 163 19.2. command illegalization table ................................................................................. 163 19.3. temporary receive data buffer .............................................................................. 168 19.4. descriptor table ...................................................................................................... 168 19.4.1. receive subaddress control word ..................................................................... 171 19.4.2. transmit subaddress control word .................................................................... 174 19.4.3. data buffer options for mode code commands ................................................. 176 19.4.4. receive mode control word ............................................................................... 177 19.4.5. transmit mode control word ............................................................................... 179 20. remote terminal rt1 and rt2 message data buffers ............... 183 20.1. subaddress message information words .............................................................. 184 20.1.1. receive subaddress command ......................................................................... 184 20.1.2. transmit subaddress command ........................................................................ 186 20.2. mode command message information words ....................................................... 187 20.2.1. receive mode command ................................................................................... 188 20.2.2. transmit mode command .................................................................................. 189 HI-6130, hi-6131
holt integrated circuits 9 20.3. ping-pong data buffering ....................................................................................... 191 20.3.1. double buffered (ping-pong) mode .................................................................... 191 20.3.2. ping-pong enable / disable handshake ............................................................. 192 20.3.3. broadcast message handling in ping-pong mode .............................................. 194 20.4. indexed data buffer mode ...................................................................................... 196 20.4.1. single message mode ......................................................................................... 196 20.4.2. broadcast message handling in index mode ...................................................... 196 20.5. circular buffer mode 1 ............................................................................................ 200 20.6. circular buffer mode 2 ............................................................................................ 204 21. remote terminal rt1 and rt2 mode command processing .... 209 21.1. general considerations .......................................................................................... 209 21.2. mode command interrupts ..................................................................................... 209 21.3. mode command data words ................................................................................. 210 21.4. standard mode command processing ................................................................... 212 21.5. simplified mode command processing .................................................................. 212 22. serial eeprom programming utility ............................................... 214 22.1. writing the auto-initialization eeprom .................................................................. 214 22.2. overall 32k word checksum used by auto-initialization ....................................... 216 23. reset and initialization ........................................................................ 218 23.1. hardware master reset and optional auto-initialization ........................................ 218 23.2. memory test fail address register (0x0024) ....................................................... 221 23.3. software reset ....................................................................................................... 222 23.3.1. remote terminal 1 (rt1) .................................................................................... 222 23.3.2. remote terminal 2 (rt2) .................................................................................... 223 23.3.3. bus monitor smt / imt ........................................................................................ 224 24. self-test .................................................................................................... 226 24.1. optional ram self-test after hardware master reset ........................................... 226 24.2. host-directed self-test ........................................................................................... 226 24.2.1. self-test control register (0x0028) ................................................................. 226 24.2.2. loopback test transmit data register (0x001f) .............................................. 230 24.2.3. loopback test receive data register (0x0002) ............................................... 230 24.2.4. ram self-test fail address register (0x001b) ................................................. 230 24.2.5. host-directed ram self-test ............................................................................... 231 24.2.6. host-directed rt-mode loopback testing (on-line analog or off-line digital) 231 HI-6130, hi-6131
holt integrated circuits 10 24.2.7. programmed bc-mode digital loopback testing (off-line) .............................. 232 24.2.8. continuous bc-mode analog loopback testing (on-line) ................................ 232 25. host interface ........................................................................................ 233 25.1. HI-6130 host bus interface ..................................................................................... 233 25.1.1. bus wait states and data prefetch ..................................................................... 233 25.2. hi-6131 serial peripheral interface ......................................................................... 234 25.2.1. serial peripheral interface (spi) basics ............................................................. 234 25.2.2. hi-6131 spi commands ...................................................................................... 235 25.2.3. fast-access commands for registers 0-15 ....................................................... 235 25.2.4. fast-access write commands for registers 0-63 ............................................. 235 25.2.5. indirect addressing of ram and registers ......................................................... 236 25.2.6. data prefetch for spi read cycles .................................................................... 238 25.2.7. special purpose commands .............................................................................. 239 25.2.8. rt descriptor table prefetch exceptions ........................................................... 241 26. appendix: rt messages responses, options & exceptions ... 245 27. electrical characteristics .............................................................. 272 27.1. absolute maximum ratings .................................................................................... 272 27.2. recommended operating conditions ..................................................................... 272 27.3. dc electrical characteristics .................................................................................. 272 27.4. ac electrical characteristics D hi-6131 host bus interface timing ...................... 274 27.5. ac electrical characteristics D HI-6130 host bus interface timing ...................... 275 28. mil-std-1553 bus interface .................................................................. 280 29. thermal characteristics ................................................................... 281 30. additional pin / package configurations ..................................... 281 30.1. hi-6131pcx (64-pin qfn) ...................................................................................... 281 30.2. hi-6131pqx (64-pin pqfp) .................................................................................... 282 30.3. hi-6132cxx (121bga, 121lga or 121pga) .......................................................... 283 31. ordering information .......................................................................... 284 32. revision history ..................................................................................... 286 33. package dimensions .............................................................................. 288 HI-6130, hi-6131
holt integrated circuits 11 list of figures figure 1. block diagram .............................................................................................................. 14 figure 2. address mapping for registers and ram .................................................................... 21 figure 3. fixed address mapping for interrupt log buffer ........................................................... 39 figure 4. bus controller message sequence structures ............................................................. 52 figure 5. bus controller flag operation ...................................................................................... 62 figure 6. structure of bus controller message control / status blocks in ram ......................... 64 figure 7. simple monitor terminal (smt) data storage .............................................................. 97 figure 8. deriving the monitor filter table address from the received command word ......... 101 figure 9. irig-106 data packet and message storage summary ............................................. 115 figure 10. deriving the monitor filter table address from the received command word ....... 123 figure 11. irig-106 data fields and message storage ............................................................ 124 figure 12. mil-std-1553 command word structure ............................................................... 161 figure 13. deriving the illegalization table address from the received command word ....... 165 figure 14. address mapping for illegalization table ................................................................. 166 figure 15. summary of rt1 illegalization table addresses for mode code commands ......... 167 figure 16. address mapping for rt1 descriptor table ............................................................. 170 figure 17. deriving a descriptor table control word address from command word ............. 171 figure 18. illustration of ping-pong buffer mode ...................................................................... 193 figure 19. ping-pong buffer mode example for a receive subaddress .................................. 195 figure 20. illustration of indexed buffer mode .......................................................................... 198 figure 21. indexed buffer mode example for a receive subaddress (broadcast disabled) .... 199 figure 22. illustration of circular buffer mode 1 ........................................................................ 202 figure 23. circular buffer mode 1 example for a receive subaddress ................................... 203 figure 24. illustration of circular buffer mode 2 ........................................................................ 207 figure 25. circular buffer mode 2 example for a receive subaddress ................................... 208 HI-6130, hi-6131
holt integrated circuits 12 figure 26. generalized single-byte transfer using spi protocol. sck is shown for spi modes 0 and 3 ..................................................................... 235 figure 27. single-word (2-byte) read from ram or a register .............................................. 237 figure 28. single-word (2-byte) write to ram or a register .................................................. 237 figure 29. hi-6131 host bus interface timing diagram ............................................................ 274 figure 30. register and ram write operations for btype = 1 ................................................ 276 figure 31. register and ram write operations for btype = 0 ................................................ 277 figure 32. register and ram read operations for btype = 1 ................................................ 278 figure 33. register and ram read operations for btype = 0 ................................................ 279 figure 34. mil-std-1553 direct coupled test circuits ............................................................. 280 figure 35. mil-std-1553 transformer coupled test circuits ................................................... 280 HI-6130, hi-6131
holt integrated circuits 13 list of tables table 1. common pins (apply to all devices) ............................................................................... 16 table 2. pins that apply to HI-6130 or hi-6132 only (host parallel bus interface) ....................... 19 table 3. pins that apply to hi-6131 or hi-6132 only (host spi bus interface) ............................. 20 table 4. pins that apply to hi-6132 only (selectable 16-bit parallel bus or spi host interface) ... 20 table 5. register summary ......................................................................................................... 25 table 6. bus controller condition code table ............................................................................. 53 table 7. bus controller instruction op codes .............................................................................. 56 table 8. effect of broadcast command received rt status bit on status set condition ..... 82 table 9. message block in circular command buffer for smt monitor using 16-bit time tag ... 93 table 10. message block in circular command buffer for smt monitor using 48-bit time tag . 94 table 11. monitor address list for smt mode ............................................................................. 95 table 12. smt message filter table ......................................................................................... 102 table 13. imt message filter table ........................................................................................... 123 table 14. monitor address list for imt mode ............................................................................ 126 table 15. summary of data buffer modes. ............................................................................... 184 table 16. circular buffer mode 2 (initialization factors based on message block size) ............. 205 table 17. mode code command summary ............................................................................... 210 table 18. terminal unlock word encoding ................................................................................ 215 table 19. registers are not written using eeprom data .......................................................... 216 table 20. ready delay times: from mr input pin rising edge to ready output pin rising edge .... 218 table 21. rt1 soft reset summary .......................................................................................... 222 table 22. rt2 soft reset summary .......................................................................................... 223 table 23. smt / imt soft reset summary ................................................................................ 224 table 24. fast-access spi commands for lower registers .................................................... 243 table 25. spi commands using memory address pointer ........................................................ 244 HI-6130, hi-6131
holt integrated circuits 14 1. block diagram HI-6130 mil-std-1553 terminal with host parallel bus interface hi-6131 mil-std-1553 terminal with host spi interface rt 1 message processor bc message processor mt message processor rt 2 message processor bus b manchester encoder bus b manchester decoder bus a manchester encoder bus a manchester decoder reset & initializatio n logi c memory and register access control address data control discrete signal input configuration option logic t est logi c bus busb busb txinhb txinha vccp mclk ttclk internal clocks gnd vcc logic power transceiver power test mode r t2ssf ackirq r t1ssf mr r t2a4-0 aut oen r t2ap eecopy bendi ramedc r t1lock mttclk r t1a4-0 r t1ap mtst off r t2lock r t1ena r t2ena bcena bus/spi (hi-6132 only) mtrun host bus interface HI-6130 onl y ir q mtpkrdy ready active ce r/ or ww e str oe or a0 /l b wa it or wa it d15:0 a15: 1 btype bwid wpol r t1mc8 r t2mc8 discret e signal output s host interface spi hi-6131 onl y sck si so ce addres s data control addres s dat a contro l static ram and registers address dat a contro l serial peripheral interface (spi )t o eeprom optional serial eeprom (auto-config) ecs esck mosi miso addres s dat a contro l tx 1553 w ords rx 1553 w ords addres s & contro l wo rd s bctrig bus busa busa HI-6130 or hi-6132 only hi-6131 or hi-6132 only figure 1. block diagram HI-6130, hi-6131
holt integrated circuits 15 2. feature overview 2.1. bus controller operation the hi-613x is confgurable to operate as a bus controller (bc). the bc is a programmable message-sequencing device for control in mil-std-1553b applications. programmed using a set of 28 instruction op codes, the bc greatly reduces the hosts processing workload. the bc can optionally use a 16- or a 32-bit time base, clocked from a choice of six internally generated clocks, or an external time base clock. special bc op codes manage all 32-bit time base functions. the programmable hi-613x bus controller autonomously supports multi-frame message scheduling, message retry schemes, storage of message data, asynchronous message insertion and status /error reporting to the host processor. 2.2. remote terminal operation the hi-613x is confgurable to operate one as or two remote terminals. the rts are modeled after the popular holt hi-6120/21 remote terminal. the two remote terminals operate with independent characteristics, each rt having fully separate ram structures (e.g., descriptor and illegal command tables) and independent confguration and status registers. ram buffer options include single, double and 2 circular buffer choices. the two rts can be reset and reinitialized independently. the full beneft of two autonomous rts is achieved while using the same complexity and circuit board area as a single remote terminal. 2.3. monitor terminal operation message commands, terminal responses and message data are stored in internal ram, using one of two possible modes. simple monitor terminal (smt) and irig monitor terminal (imt) modes are targeted for different applications. when operating in smt mode, the mt records commands and data separately. the smt can utilize 16- or 48-bit time tags with a range of clocking options. the imt mode operation is designed to meet data recording requirements of telemetry standard rcc document 106-07, chapter 10. this irig 106 chapter 10 data recorder uses 48-bit relative time stamping, having 10mhz (100ns) resolution. message time stamps occur at one of three selectable message progress points. several error handling schemes are available. bus monitor interrupts notify the host when circular buffer rollover occurs, or when a user-programmed buffer level has been reached. the imt stores message records in the assigned buffer using irig 106 packet body format. the device can optionally generate complete irig 106 packets, including full packet headers and trailers meeting irig 106 chapter 10 requirements. 2.4. interrupts host interrupts can originate from device hardware or any of the enabled terminal devices (up to 4 devices). a circular 64-word interrupt log buffer retains interrupt information from the last 32 interrupts, while the hardware maintains a count of occurring interrupts since the previous host buffer service. hardware-assisted interrupt decoding provides quick identifcation of the interrupt source by terminal device: bc, mt, rt1, rt2 or hardware. when a hardware interrupt occurs (e.g., bus a loopback failure), a pending hardware interrupt register bit explicitly identifes the interrupt source. for interrupts from bc, mt or rt, the three low-order bits in the same register identify the specifc interrupt register (or registers) with pending interrupts: that is, the bc, mt or rt pending interrupt registers. 2.5. reset and initialization after hardware master reset, there are two hi- 613x initialization methods: host initialization or self- initialization from external serial eeprom. for host initialization, the host processor uses its bus interface or 4-wire spi to load hi-613x registers and initialize tables, data buffers, etc. in internal static ram. for self- initialization, the device uses setup information contained within an external serial eeprom. a dedicated 4-wire spi port reads data from the serial eeprom and writes it to registers and ram. error checking is performed, looking for data mismatch or an eeprom checksum error. individual 1553 terminal devices (bc, mt, rt1 or rt2) can be re-initialized from the serial eeprom by writing to the reset initialization register. HI-6130, hi-6131
holt integrated circuits 16 3. pin descriptions table 1. common pins (apply to all devices) pin function description mclk input 50k pull-down master clock input, 50.0mhz +/-100 ppm. ttclk mttclk inputs 50k pull-down optional clock input for bc time base and rt time tag counters. optional clock input for the mt time tag counter. each function (bc, mt, rt1, rt2) has an independent time tag counter. the bc and rt counters share a common clock, selectable from internally generated frequencies, or an external clock input. the mt time tag counter has its own external or internal clock source. mr input 50k pull-up master reset, active low. the host can also assert software reset by setting bits in the master status & reset register. txinha txinhb inputs 50k pull-down transmit inhibit inputs for bus a and bus b, active high. these two inputs are logically ored with the pair of corresponding bits in the master confguration register to enable or inhibit transmit on bus a or bus b, affecting behavior for all enabled 1553 devices. mtstoff input 50k pull-down memory test disable, active high. when this pin is low, the device performs a memory test on the entire ram after rising edge on the mr reset pin. when this pin is high, ram testing is skipped, resulting in a faster reset process. for further information, refer to section 23 . autoen input 50k pull-down auto-initialize enable, active high. if this pin is high at rising edge on mr reset pin, self-initialization proceeds, copying confguration data to registers and ram from an external serial eeprom via a dedicated eeprom spl port. refer to section 23 . ready output this pin is low when auto-initialization or built-in test is in process. the host cannot read or write device ram or registers when pin state is low; reads to any address return the value in the master status & reset register. when the autoen pin is low at master reset, the host can confgure device ram and registers after ready goes high. active output this pin is high while an enabled bc or rt in the device is processing a 1553 message. the imta bit 1 in master confguration register 0x0000 logically- ors bus monitor (mt) activity as well. ecs esck mosi miso output output output input 50k pull-down dedicated 4-wire serial peripheral interface (spi) for connection to an optional external eeprom used for automatic self-initialization when autoen is high at master reset. eecopy input 50k pull-down eeprom copy, active high. asserting this input initiates ram and register copy into serial eeprom used for auto-initialization. refer to section 23 . bcena input 50k pull-down bus controller enable input, active high. HI-6130, hi-6131
holt integrated circuits 17 pin function description bctrig input 50k pull-down bc trigger input, active high. used in conjunction with certain bc instructions. mtrun input 50k pull-down monitor run / stop input, active high. this input starts/stops mt data recording. upon going low, the mt stops when the current message is completed. rt1ena rt2ena inputs 50k pull-down rt1 and rt2 enable input pins, active high. these inputs are logically anded with the corresponding rt1ena and rt2ena bits in master confguration register 0x0000. the anded result must be high before initializing rt descriptor tables, and must be high when the master confguration register rt1stex or rt2stex start execution bits are asserted to begin rt1 or rt2 operation. rt1lock rt2lock inputs 50k pull-down pin states are latched to the lock bit in the rtx operational status register when rising edge occurs on the mr pin. if status register lock bit is high, the host cannot overwrite the terminal address in the same register. if status register lock bit is low, the host can overwrite the terminal address and parity (and the lock bit) in the rtx operational status register. rt1mc8 rt2mc8 outputs remote terminal reset rt mode command (mc8) received. this active low output is asserted at status word completion when rt1 or rt2 received a reset remote terminal mode code command. the minimum output pulse width is 100ns, unaffected by mr assertion. rt1ssf rt2ssf inputs 50k pull-down rt subsystem fail input, active high. when this input is high, the selected rt1 or rt2 sets the subsys fag in its transmit status word. this input is logically- ored with the same bit in the terminals rt1 or rt2 1553 status word bits register. mtpkrdy output monitor packet ready output, active high. this pin is asserted when a message data packet is complete, as defned by the various mt confguration registers (maximum word or message count, maximum packet time, etc.) assertion of this bit indicates the mt has stopped. irq output interrupt request, active low. this pin is asserted each time an enabled interrupt event occurs. this signal is programmed as a brief low-going pulse output or as a level output by the intsel bit in the master confguration register. if level output is selected, irq stays low until the host acknowledges irq by pulsing a rising edge at the ackirq pin. ackirq input 50k pull-down interrupt acknowledge, active high. this input is only used when the intsel bit in the rt confguration register is high, enabling level interrupt assertion for the irq pin. when interrupt assertion causes the irq pin to go low, a high-going pulse on ackirq (250ns minimum duration) clears the irq output to logic 1. rt1a4:0 rt1ap rt2a4:0 rt2ap inputs 50k pull-ups remote terminal address bits 4 - 0, and parity bit for rt1 and rt2. the rtap pin provides odd parity for the address on pins rta4:0. the terminal address and parity pin levels are latched into the respective rt operational status registers when rising edge occurs on the mr pin. the rt operational status register value (not these pins) refects the active terminal address. the host can overwrite the rt operational status register address value only when the register lock bit is reset. HI-6130, hi-6131
holt integrated circuits 18 pin function description bendi input 50k pull-up big endian confguration pin for selecting endianness or byte order, when using byte transfers. endianness is the system attribute that indicates whether integers are represented with the most signifcant byte stored at the lowest address (big endian) or at the highest address (little endian). internal register / ram storage is big endian. when using the HI-6130, this pin only applies when the host parallel bus is confgured for 8-bit width, that is, when bwid equals 0. when the HI-6130 is confgured for 16-bit bus width, the bendi input pin is dont care. when using the hi-6131, this pin controls the byte order of transferred 16-bit data following the spi command. when bendi is low, little endian is chosen; the low order byte (bits 7:0) is transacted on the spi before the high order byte (bits 15:8). when bendi is high, big endian is chosen and the high order byte is transacted on the spi before the low order byte. ramedc input 50k pull-down ram edc (error detection / correction) enable. when pin is low, device operates with 32k word ram address space, edc disabled. when pin is high, device operates with 24k word ram address space with edc enabled. all single-bit ram read errors are automatically corrected. the corrected errors and uncorrectable multi-bit ram read errors can generate separate, optional interrupts. test input 50k pull-down test enable input. the host asserts this pin to perform ram self-test and loop- back tests. mode input 50k pull-up pin used for factory test. do not connect. vcc vccp gnd power supply 3.3vdc power supply for logic and bus transceiver. busa busa analog bi-directional bus a interface to external mil-std-1553 isolation transformer. observe positive / negative polarity. busb busb analog bi-directional bus b interface to external mil-std-1553 isolation transformer. observe positive / negative polarity. HI-6130, hi-6131
holt integrated circuits 19 table 2. pins that apply to HI-6130 or hi-6132 only (host parallel bus interface) pin function description ce input 50k pull-up chip enable, active low. when asserted, this pin enables host read or write accesses to device ram or registers using the hosts parallel bus interface. this pin is normally connected to a chip select output from the hosts bus interface. d15:0 in / out 50k pull-down tri-state data bus for host read/write operations upon registers and shared ram. all bus read/write operations transact 16 bit words, but bus width can be confgured for 8 or 16 bits. for 8-bit bus width, pins d15:8 are not connected. sixteen-bit words are transacted over an 8-bit bus as a pair of byte operations, with data presented sequentially on pins d7:0. for compatibility with different host processors when 8-bit bus width is enabled, the bendi input determines whether the low order byte is transferred before the high order byte, or vice versa. a15:1 a0 / lb input 50k pull-up address bus for host read/write operations upon registers and shared ram. when using 16-bit bus width, address bit a0 / ( lb ) from the host is not used. for 8-bit bus width, output a0 equals 0 during the frst byte read/write access; and equals 1 during the second byte access. bwid input 50k pull-up confguration pin for host bus width. high selects 16-bit bus width, low selects 8-bit bus width. btype input 50k pull-up confguration pin for host bus read/write control signal style. high selects intel style using separate read strobe oe (output enable) and write strobe we . low selects motorola style using single active-low read/write strobe str and read/ write select signal, r/ w . r/ w / we input 50k pull-up read/write direction signal r/ w when btype pin is low. active-low write enable we when btype pin is high. used for host read or write accesses to device ram or registers. this pin or the ce pin should be high during all address transitions. str / oe input 50k pull-up active-low common read/write strobe str when btype pin is low. active-low output enable oe when btype pin is high. used for host read or write accesses to device ram or registers. wpol input 50k pull-up confguration pin for wait output polarity. when the wpol pin is low, the wait output is active low ( wait ). when wpol is high, the wait output is active high (wait). HI-6130, hi-6131
holt integrated circuits 20 pin function description wait / wait output host bus read cycle wait or wait output. the HI-6130 wpol input pin sets the active level for this wait output. read cycles are slower than write cycles, but prefetching speeds data availability for multi-word sequential address read cycles. for every new bus read cycle, the HI-6130 asserts wait. connected to the processor wait or wait input, this action inserts one or more processor wait states (depending on processor clock frequency) while the HI-6130 fetches the frst word. after reading each HI-6130 register or ram address, the device prefetches and retains data from the next address. if the next bus access reads that sequential address, the data is ready without wait assertion, even if that read cycle occurs some time later. while the prefetch chain is broken by any write cycle, each read cycle prefetches and retains data from the next address, whether or not it is needed. thus wait assertion only occurs for the frst word read. the wait output is useful when the host processor runs at high clock rates and/ or when processor read wait states do not provide adequate timing margin for worst case (slowest) read cycle timing for the HI-6130. using the wait output for the slow, frst read cycle means the processor bus interface can be optimized to use faster no-wait cycles for write operations, and for reading words 2 through n in successive address, n-word read operations. processors lacking a wait or wait input pin are typically confgured to insert a fxed number of wait states for every read/write cycle. table 3. pins that apply to hi-6131 or hi-6132 only (host spi bus interface) pin function description ce input 50k pull-up chip enable, active low. when asserted, this pin enables host read or write accesses to device ram or registers via host spi port. the hi-6131 spi port operates in slave mode. this pin is connected to the slave select output on the host spi port. so output serial peripheral interface (spi) serial output pin. this pin is connected to miso (master in - slave out) pin on host spi port. the so pin is tri-stated when not transmitting serial data to the host. si input 50k pull-down serial peripheral interface (spi) serial input pin. this pin is connected to mosi (master out - slave in) pin on host spi port. sck input 50k pull-down serial peripheral interface (spi) serial clock pin. this pin is connected to sck output pin on host spi port. table 4. pins that apply to hi-6132 only (selectable 16-bit parallel bus or spi host interface) pin function description bus / spi input 50k pull-up selects 16-bit wide parallel bus or spi operation HI-6130, hi-6131
holt integrated circuits 21 4. memory map 0x0400 0x0300 0x0000 0x03ff 0x01ff 0x7fff rt2 illegalization table. initialized by the host, this table identifies illegal commands. 256 words rt1 illegalization table. initialized by the host, this table identifies illegal commands. 256 words expanded at right host-allocated static ram. comprising 94% of the memory address space, this ram is allocated for use by the enabled terminal devices. rt2 descriptor table. defines terminal behavior for valid commands: how data is stored, host interrupts, etc. 512 words multiple descriptor tables can be used for fast context switching. the active descriptor table is defined by the descriptor table base address register. rt1 descriptor table. defines terminal behavior for valid commands: how data is stored, host interrupts, etc. 512 words multiple descriptor tables can be used for fast context switching. the active descriptor table is defined by the descriptor table base address register. 0x0800 0x05ff 0x0600 0x07ff 0x0200 0x02ff 0x0180 0x01ff 0x01bf interrupt log data buffer. 64 words 0x0000 0x004f registers (listed in table 4) 80 locations 0x01e0 0x0053 reserved. 4 words 0x0050 0x0085 mt temporary buffer a. 42 words mt temporary buffer b. 42 words 0x005c 0x00af 0x0086 0x00b7 mt address list a. 8 words mt address list b. 8 words 0x00b0 0x00bf 0x00b8 0x01df rt1 temporary receive buffer. 32 words rt2 temporary receive buffer. 32 words 0x01c0 0x0100 0x017f bc general purpose queue. 64 words mt message filter table. 128 words 0x00c0 0x00ff 0x005b bc call stack. 8 words 0x0054 figure 2. address mapping for registers and ram HI-6130, hi-6131
holt integrated circuits 22 5. ram structures figure 2 shows a memory map for hi-613x memory and registers. application requirements dictate the specifc ram structures needed. these structures listed here are explained later. 5.1. interrupt log data buffer the device maintains information from the last 32 interrupts in a 64-word circular buffer in ram known as the interrupt log. two 16-bit words characterize each interrupt; one word identifes the interrupt type (interrupt identifcation word) and one word identifes the command that generated the interrupt (interrupt address word). after reset, the interrupt log address register contains the fxed buffer start address of 0x0180. after each occurring interrupt, the device updates the register to point to the log address used for the next occurring interrupt. 5.2. bus controller (bc) instruction list bc message sequencing uses an instruction list, comprised of multiple 2-word entries. each entry consists of an instruction word (op code plus execution condition code) followed by a parameter word. some op codes execute unconditionally, but most are conditional, and execute only if the condition code specifed in the instruction word tests true. this architecture provides fexibility for message frame scheduling and autonomous bc program execution, based on various conditions. 5.3. bus controller (bc) msg control / status stack referenced when a bc instruction list parameter is an address pointer, the message control status stack consists of 8- or 16-word control blocks for individual mil-std-1553 messages. within the message control/ status block, execution parameters are provided including inter-message gap, message format, active bus, message command word(s), then address pointer to a message data block in ram (when the command includes data) and the expected rt status response. 5.4. bus controller (bc) call stack when the bus controller executes a subroutine call op code, the bc subroutine call stack stores the list address for the next op code, to be executed upon return from subroutine. the bc call stack allows 8 levels of nesting. 5.5. bus controller (bc) general purpose queue the bus controller general purpose queue provides a convenient way for the bc to convey information to the external host. numerous bc op codes push various data onto the queue, including time tag count, data values, message block status word or the data at specifc ram address locations. 5.6. monitor terminal temporary buffers a & b the hi-613x monitor terminal (mt) has one 42 word receive buffer for each bus. received command words, status words and data words are temporarily stored in these buffers. at message completion, the recorded data is copied to monitor terminal buffer(s). 5.7. monitor terminal (mt) address list the monitor address list contains user-written ram addresses assigning buffer start and end addresses, and buffer utilization interrupt addresses. it also has device-maintained data buffer pointer(s). 5.8. monitor terminal (mt) message filter table this 128-word table is optionally used to selectively monitor mil-std-1553 messages based on each commands rt address and subaddress, and the transmit/receive bit status. 5.9. monitor terminal (mt) data buffers for bus monitor applications, there are two operating modes: the smt simple monitor stores command and data words in separate ram buffers. the imt irig- 106 monitor stores all information in a single ram data buffer, with or without formatted packet header and trailer. for both, the monitor address list assigns ram buffer boundaries. 5.10. rt1 and rt2 command illegalization tables for each rt, optional illegal command detection utilizes this table in ram. the table can illegalize any logical combination of 11 command word bits comprising subaddress, the transmit/receive bit and word count (or mode code), plus broadcast vs non-broadcast status, HI-6130, hi-6131
holt integrated circuits 23 resulting in a total of 4,096 possible combinations. terminal response to an illegal command sets message error status and transmits status word only. if illegal command detection is not used (that is, no illegal entries in illegalization table), the terminal responds in form to all valid commands. 5.11. rt1 and rt2 descriptor tables for each rt, a host-initialized descriptor table in ram defnes how the terminal responds to valid commands. the table is comprised of 128 four-word descriptor blocks. each of 32 subaddresses and 32 mode code values has one descriptor block for transmit and another for receive. the descriptor table defnes message options (interrupt selections, data buffer mode, etc.) and contains pointers to allocated data storage in ram. 5.12. rt1 and rt2 temporary receive buffers remote terminals rt1 and rt2 temporarily store command and data words during message transaction. at successful message completion, all data is transferred to assigned subaddress buffers. this strategy prevents valid data from being overwritten by incomplete or bad data from a later message ending in error. 5.13. rt message data buffers ordinary transmit and receive commands transact from 1 to 32 data words. the host allocates space in ram for storing transacted message data words as well as message information words. 5.14. rt storage for mode code commands in addition to commands used for data transmit and receive, mil-std-1553 also defnes mode code commands for command and control. these mode commands transfer a single data word, or no data word at all. the user has the option for storing mode command data in ram buffers assigned in the descriptor table, or stored within the rt descriptor table itself. the second option is often preferred for its simplicity. 6. hardware features 6.1. remote terminal address inputs the 5-bit remote terminal address is set using pins rta4:0. the rtap input pin should be set or reset to present matching odd parity. the state of the rt address and parity pins is latched into the rt operational status register upon rising edge on the mr master reset input. the state of the lock input is latched into the rt operational status register at the same time, and controls whether or not the active terminal address and parity in the rt operational status register can be overwritten by host writes into the register. when the lock input pin is high, autoinitialization cannot overwrite the rt address value latched from the input pins. between master reset assertions, the state of the rta and rtap input pins is dont care. if the value of rt address and parity in the rt operational status register has parity error, terminal operation is disabled. 6.2. dual transceivers for mil-std-1553 bus built-in bus transceivers provide direct interface between the device and mil-std-1553 bus isolation transformers. the transceivers convert digital data to and from differential manchester ii encoded bus signals. a pair of transmit inhibit input pins exercises direct control over transmission for both buses. 6.3. encoder and decoders the device uses separate manchester ii encoders and decoders for each bus. decoders check for proper sync pulse and manchester waveform, edge skew, correct number of bits and parity. encoders are used for transmission. during transmit, each encoded word is looped back through the bus decoder for error checking. receiver bus sampling is clocked at 50 mhz, providing excellent tolerance to zero-crossing distortion. 6.4. auto-initialization serial eeprom interface the device has an automatic self-initialization feature. if self-initialization is enabled after mr master reset, the device reads confguration settings from an external serial eeprom to initialize registers and ram structures. a method is provided to initially program or later modify the external serial eeprom by copying host-loaded tables and register values to the serial eeprom. HI-6130, hi-6131
holt integrated circuits 24 6.5. selection of host interface (hi-6132 only) the hi-6132 (hermetic ceramic bga package) provides the option of a selectable host interface using the spi/ bus pin. ? bus/ spi pin set to logic 1: selects 16-bit parallel bus host interface ? bus/ spi pin reset to logic 0: selects spi host interface 7. register & memory addressing the hi-613x has an internal address space of 32k 16-bit words. registers occupy the low 80 locations in this address space. in this data sheet, register / ram addresses are expressed as hexadecimal numbers, using the c programming convention where the prefx 0x denotes a hexadecimal value; e.g., 0x00ff represents 00ff hex. figure 2 shows address mapping for registers and ram. all registers and some ram structures have fxed addresses. other ram structures shown are relocatable; each relocatable structure has a base address register. figure 2 shows the default locations for relocatable structures. ram allocations for unused mil-std-1553 functions can be reassigned as needed. for example, an application using just a bus monitor can reassign all bc and rt ram for monitor needs. device ram and register address mapping is word oriented, rather than byte oriented. register and memory addresses throughout this document refect word addressing. for all parallel bus-interface applications (HI-6130) and most spi interface applications (hi- 6131), word oriented addressing applies. word oriented addressing uses address inputs a15 to a1; address input a0 is not used. fifteen bits are suffcient for a 32k address range. 7.1. 8-bit bus operation: (HI-6130 only) when required by the application, parallel bus interface HI-6130 devices can use byte transfers. all 8-bit microprocessors (and some 16-bit and 32-bit microprocessors) use (or can use) byte-oriented memory accesses. to provide byte capability, the HI-6130 uses the sixteenth bus address input, a0. thus 16 address pins a15:0 address 64k bytes. the a0 input denotes whether the frst or second byte in the word is being addressed, while a15-a1 indicate the word address. this difference must be considered when assigning HI-6130 pointer values or accessing ram or registers. from the microprocessors standpoint, any host-assigned ram buffer address will be double the value of the buffers pointer stored in ram. this paragraph only applies to HI-6130 using 8-bit bus width. from this point on, all register and memory addresses presented in this data sheet are 15-bit word addresses. from the host standpoint, register operations and ram operations are performed identically. depending on function, individual registers may be read-only, read- write, or a combination of read-only and read-write bit felds. read-only registers and read-only register bit felds, are protected against accidental host overwrite by device logic. addresses in the range 0x004c to 0x7fff apply to static ram memory. all ram is read-write and can be written or read by either the host or the internal device logic. both host and the device update certain ram locations (e.g., rt descriptor table control words). these locations are protected against accidental data collision by arbitration logic which acts when concurrent writes by both host and device occur. 8. register definitions residing at the start of the memory address space, 80 addresses are reserved for hi-613x registers. register addresses overlay the shared ram address space. register bits are active high and bit 15 is the most signifcant. table 5 lists all device registers. HI-6130, hi-6131
holt integrated circuits 25 table 5. register summary register number hex address used by register name hard reset default 0 0x0000 all master confguration register ( page 29 ) 0x0000 1 0x0001 all master status and reset register ( page 33 ) 0x0000 2 0x0002 rt1 rt1 current command register ( page 150 ) 0x0000 3 0x0003 rt1 rt1 current control word address register ( page 150 ) 0x0000 4 0x0004 rt2 rt2 current command register ( page 150 ) 0x0000 5 0x0005 rt2 rt2 current control word address register ( page 150 ) 0x0000 6 0x0006 all hardware pending interrupt register ( page 40 ) 0x0000 7 0x0007 bc bc pending interrupt register ( page 90 ) 0x0000 8 0x0008 mt smt pending interrupt register ( page 111 ) imt pending interrupt register ( page 140 ) 0x0000 9 0x0009 rt1/rt2 rt1 & rt2 pending interrupt register ( page 158 ) 0x0000 10 0x000a all interrupt count & log address register ( page 37 ) 0x0180 11 0x000b all memory address pointer 1 (hi-6131 only) ( page 49 ) 0x0000 12 0x000c all memory address pointer 2 (hi-6131 only) ( page 49 ) 0x0000 13 0x000d all memory address pointer 3 (hi-6131 only) ( page 49 ) 0x0000 14 0x000e all memory address pointer 4 (hi-6131 only) ( page 49 ) 0x0000 15 0x000f all hardware interrupt enable register ( page 40 ) 0x6000 16 0x0010 bc bc interrupt enable register ( page 90 ) 0x6000 17 0x0011 mt smt interrupt enable register ( page 111 ) imt interrupt enable register ( page 140 ) 0x6000 18 0x0012 rt/rt2 rt1 & rt2 interrupt enable register ( page 158 ) 0x6000 19 0x0013 all hardware interrupt output enable register ( page 40 ) 0x6000 20 0x0014 bc bc interrupt output enable register ( page 90 ) 0x0000 21 0x0015 mt smt interrupt output enable register ( page 111 ) imt interrupt output enable register ( page 140 ) 0x0000 22 0x0016 rt1/rt2 rt1 & rt2 interrupt output enable register ( page 158 ) 0x0000 23 0x0017 rt1 rt1 confguration register ( page 144 ) 0x0000 24 0x0018 rt1 rt1 operational status register ( page 148 ) 0x0000 25 0x0019 rt1 rt1 descriptor table base address register ( page 150 ) 0x0400 26 0x001a rt1 rt1 1553 status word bits register ( page 151 ) 0x0000 HI-6130, hi-6131
holt integrated circuits 26 register number hex address used by register name hard reset default 27 0x001b rt1 rt1 current message info word register ( page 152 ) 0x0000 28 0x001c rt1 rt1 bus a select register ( page 153 ) 0x0000 29 0x001d rt1 rt1 bus b select register ( page 153 ) 0x0000 30 0x001e rt1 rt1 built-in test (bit) word register ( page 154 ) 0x0000 31 0x001f rt1 rt1 alternate bit word register ( page 155 ) 0x0000 32 0x0020 rt2 rt2 confguration register ( page 144 ) 0x0000 33 0x0021 rt2 rt2 operational status register ( page 148 ) 0x0000 34 0x0022 rt2 rt2 descriptor table base address register ( page 150 ) 0x0600 35 0x0023 rt2 rt2 1553 status word bits register ( page 151 ) 0x0000 36 0x0024 rt2 rt2 current message info word register ( page 152 ) 0x0000 37 0x0025 rt2 rt2 bus a select register ( page 153 ) 0x0000 38 0x0026 rt2 rt2 bus b select register ( page 153 ) 0x0000 39 0x0027 rt2 rt2 built-in test (bit) word register ( page 154 ) 0x0000 40 0x0028 rt2 rt2 alt. bit word register ( page 155 ) 0x0000 41 0x0029 mt smt (bus monitor) confguration register ( page 103 ) imt (bus monitor) confguration register ( page 128 ) 0x0800 42 0x002a mt imt packet maximum message count ( page 133 ) 0x0000 43 0x002b mt imt packet maximum 1553 word count ( page 133 ) 0x0000 44 0x002c mt imt packet maximum time ( page 134 ) 0x0000 45 0x002d mt imt packet maximum gap time ( page 134 ) 0x0000 46 0x002e mt imt channel id register ( page 135 ) 0x0000 47 0x002f mt smt address list start address register ( page 106 ) imt address list start address register ( page 132 ) 0x0060 48 0x0030 mt smt next message buffer address pointer ( page 106 ) imt next message buffer address pointer ( page 132 ) 0x0000 49 0x0031 mt smt last message buffer address register ( page 107 ) imt last message buffer address register ( page 132 ) 0x0000 50 0x0032 bc bc confguration register ( page 73 ) 0x0000 51 0x0033 bc start address register for bc instruction list ( page 82 ) 0x0000 52 0x0034 bc bc instruction list pointer ( page 82 ) 0x0000 53 0x0035 bc bc frame time remaining register ( page 83 ) 0x0000 54 0x0036 bc bc time to next message register ( page 83 ) 0x0000 HI-6130, hi-6131
holt integrated circuits 27 register number hex address used by register name hard reset default 55 0x0037 bc bc condition code ( page 83 ) bc general purpose flag register ( page 86 ) 0x0000 56 0x0038 bc bc general purpose queue pointer register ( page 86 ) 0x00c0 57 0x0039 all time tag counter confguration register ( page 45 ) 0x0000 58 0x003a mt smt time tag counter low ( page 107 ) imt time tag counter low ( page 136 ) 0x0000 59 0x003b mt smt time tag counter mid ( page 107 ) imt time tag counter mid ( page 136 ) 0x0000 60 0x003c mt smt time tag counter high ( page 107 ) imt time tag counter high ( page 136 ) 0x0000 61 0x003d mt smt time tag utility register low (count load or capture) ( page 108 ) imt time tag utility register low (count load or capture) ( page 136 ) 0x0000 62 0x003e mt smt time tag utility register mid (count load or capture) ( page 108 ) imt time tag utility register mid (count load or capture) ( page 137 ) 0x0000 63 0x003f mt smt time tag utility register high (count load or capture) ( page 108 ) imt time tag utility register high (count load or capture) ( page 137 ) 0x0000 64 0x0040 mt smt time tag match register low (count match interrupt) ( page 109 ) imt time tag match register low (count match interrupt) ( page 137 ) 0x0000 65 0x0041 mt smt time tag match register mid (count match interrupt) ( page 109 ) imt time tag match register mid (count match interrupt) ( page 137 ) 0x0000 66 0x0042 mt smt time tag match register high (count match interrupt) ( page 109 ) imt time tag match register high (count match interrupt) ( page 138 ) 0x0000 67 0x0043 bc bc time tag counter low ( page 87 ) 0x0000 68 0x0044 bc bc time tag counter high ( page 87 ) 0x0000 69 0x0045 bc bc time tag utility register low (count load or capture) ( page 88 ) 0x0000 70 0x0046 bc bc time tag utility register high (count load or capture) ( page 88 ) 0x0000 71 0x0047 bc bc time tag match register low (count match interrupt) ( page 88 ) 0x0000 72 0x0048 bc bc time tag match register high (count match interrupt) ( page 88 ) 0x0000 73 0x0049 rt1 rt1 time tag counter ( page 155 ) 0x0000 74 0x004a rt1 rt1 time tag utility register (count load / count match interrupt) ( page 156 ) 0x0000 75 0x004b rt2 rt2 time tag counter ( page 155 ) 0x0000 HI-6130, hi-6131
holt integrated circuits 28 register number hex address used by register name hard reset default 76 0x004c rt2 rt2 time tag utility register (count load / count match interrupt) ( page 156 ) 0x0000 77 0x004d test factory test control register 0x0000 78 0x004e ---- checksum fail address & eeprom lock/unlock 0x0000 79 0x004f bc bc last message block address 0x0000 80 0x0050 bc default location for bc wmi address pointer 0x0000 40 * 0x0028 self-test self-test control register (when test input pin is logic 1) (see page 226 ). when test pin is logic 0, this address is an rt2 register. 0x0000 31 * 0x001f self-test loopback test transmit data register (when test input pin is logic 1) (see page 230 ). when test pin is logic 0, this address is an rt1 register. 0x0000 2 * 0x0002 self-test loopback test receive data register (when test input pin is logic 1) (see page 230 ). when test pin is logic 0, this address is an rt1 register. 0x0000 27 * 0x001b self-test ram self-test fail address register (when test input pin is logic 1) (see ram self-test fail address register (0x001b) on page 230 ). when test pin is logic 0, this address is an rt2 register. 0x0000 36 ** 0x0024 auto-init. memory test fail address register (when autoen input pin is logic 1) (see page 221 ). this is the frst ram / register address with data mismatch (see section 23.1 on page 218 ). once execution starts, register address 0x0024 is an rt2 register. 0x0000 * alternate function for these registers when test pin is logic 1. ** alternate function after reset when autoen pin is logic . register descriptions are grouped by function: bus controller, bus monitor, remote terminal. here is the presentation order: 1. registers used by all device functions (confguration, status and time tag registers), 2. bus controller registers, 3. bus controller confguration and operation, 4. bus monitor registers, 5. bus monitor confguration and operation, 6. remote terminal registers, 7. remote terminal confguration and operation HI-6130, hi-6131
holt integrated circuits 29 9. registers used by all device functions 9.1. master confguration register (0x0000) txinhb mapsel1 txinha mapsel0 ssr8 rt2ena mtena rt1stex bsdtxo bcstrt bcena rw rt1ena rt2stex mr reset host access bit 15 14 13 12 11 10 intsel reserved imta 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 8 7 6 5 4 3 2 1 0 all bits in this 16-bit register are read-write and are fully maintained by the host. this register is cleared after mr pin master reset, and is unaffected by assertion of the mtreset, rt1reset or rt2reset bits in the master status and reset register (0x0001). bit no. mnemonic r/w reset function 15 txinha r/w 0 transmit inhibit bus a. this bit is logically ored with the txinha input pin. this register bit and the corresponding txinha pin globally affect all enabled 1553 devices (bc, mt, rt). this inhibit disables all transmission on bus a. 14 txinhb r/w 0 transmit inhibit bus b. this bit is logically ored with the txinhb input pin. this register bit and the corresponding txinhb pin globally affect all enabled 1553 devices (bc, mt, rt). this inhibit disables all transmission on bus b. 13 bcstrt r/w 0 bus controller start. if the bcena input pin and bcena register bit are both logic 1, a host write which sets this bit to 1 begins bus controller operation. when written to 1, this bit self-resets to 0. this bit always reads back at logic 0 state. 12 bcena r/w 0 bus controller enable. this bit is logically anded with the bcena input pin. if either the input pin or this register bit is logic 0, bus controller operation is disabled. the bcena input pin should be connected to ground in applications not using bc mode. this bit cannot be set if bcena input pin = 0. when the bcena pin and bcena register bit are both logic 1, the bus controller device is enabled, but bc operation does not begin until bcstrt bit 13 is set. if this register bit or the bcena input pin becomes logic 0 while bc operation is underway, bc operation is immediately terminated without waiting for message completion. HI-6130, hi-6131
holt integrated circuits 30 bit no. mnemonic r/w reset function 11 ? 10 mapsel1:0 (hi-6131 only) r/w 0 map (memory address pointer) select. this 2-bit feld only applies to the hi-6131 with spi host interface. the host spi relies on a hardware memory address pointer for many spi register or ram accesses. this 2-bit feld specifes which map is active for spi transactions: register bit 11-10 0-0 0-1 1-0 1-1 active map map1 map2 map3 map4 map register address 0x000b 0x000c 0x000d 0x000e enabling spi op code 0xd8 0xd9 0xda 0xdb the full 16-bit register can be directly written by the host using spi op code 0x10, followed by 16-bit data word. an alternative method uses spi op codes 0xd8 C 0xda that write just the 2-bit mapsel feld, without affecting other register data. these four spi op codes only require transmission of an 8-bit instruction, without accompanying data. note: fast access spi op codes contain embedded register addresses and use a separate memory address pointer. this preserves values contained in map1 through map4. the fast access map cannot be read by the host but is written each time a fast access op code is processed. fast access op codes are provided for these spi operations: ? spi reads to register addresses 0 through 0x000f (decimal 15) ? spi writes to register addresses 0 through 0x003f (decimal 63) 9 ssr8 (HI-6130 only) r/w 0 single-strobe read for 8-bit parallel bus. this option only applies to HI-6130 devices with host parallel bus interface confgured for 8-bit bus width. when performing 2-byte memory read accesses, some microprocessors with 8-bit bus assert separate read_enable (or strobe ) pulses for high and low bytes. other microprocessors assert a single, wider read_enable (or strobe ) pulse, while simply changing the low address bit (a0 / lb) to access the two bytes. for this last case, the ssrd8 bit should be set when writing device confguration, before the frst register or ram read access is performed. 8 mtena r/w 0 bus monitor enable. this bit is logically anded with the mtrun input pin. if input pin or register bit equals logic 0, bus monitor operation is disabled. the mtrun input pin should be connected to ground in applications not using monitor mode. when the mtrun pin and mtena register bit are both logic 1, the bus monitor is enabled, operation commences when the receiver frst decodes mil-std-1553 activity meeting the start record criteria selected by bits 6:5 in the mt confguration register. if monitor operation is underway when the mtena register bit or mtrun input pin becomes logic 0, monitor operation stops after completion of any message already underway; monitor resumes when the mtena register bit and mtrun input pin are both logic 1. HI-6130, hi-6131
holt integrated circuits 31 bit no. mnemonic r/w reset function 7 rt2ena r/w 0 remote terminal 2 enable. this bit is logically anded with the rt2ena input pin. if input pin or register bit equals logic 0, rt2 operation is disabled. the rt2ena input pin should be connected to ground in applications not using remote terminal 2. this bit cannot be set if rt2ena input pin = 0. when the register bit and rt2ena input pin are both logic 1, remote terminal 2 is enabled, but operation is controlled by the state of the rt2stex register bit. 6 rt1ena r/w 0 remote terminal 1 enable. this bit is logically anded with the rt1ena input pin. if input pin or register bit equals logic 0, rt1 operation is disabled. the rt1ena input pin should be connected to ground in applications not using remote terminal 1. this bit cannot be set if rt1ena input pin = 0. when the register bit and rt1ena input pin are both logic 1, remote terminal 1 is enabled, but operation is controlled by the state of the rt1stex register bit. 5 rt2stex r/w 0 remote terminal 2 start execution. if register bit 7 and the rt2ena input pin are both logic 1, setting this bit begins remote terminal 2 operation. once running, resetting this bit (or the rt2ena register bit or rt2ena input pin) immediately stops rt2 operation. 4 rt1stex r/w 0 remote terminal 1 start execution. if register bit 6 and the rt1ena input pin are both logic 1, setting this bit begins remote terminal 1 operation. once running, resetting this bit (or the rt1ena register bit or rt1ena input pin) immediately stops rt1 operation. HI-6130, hi-6131
holt integrated circuits 32 bit no. mnemonic r/w reset function 3 bsdtxo r/w 0 bus shutdown transmit only. the bit only applies when remote terminal rt1 and/or rt2 is enabled. the bsdtxo bit determines how a 1553 bus inhibit works when (a) the rtxinha or rtxinhb bit is set in the rt confguration register, or (b) the rt receives a valid bus shutdown mode code command, either mc4 or mc21: ? when the bsdtxo bit is reset, logic 1 for an rtxinha or rtxinhb bit in a rt confguration register (or a bus shutdown mode command with auto shutdown enabled) inhibits both transmit and receive on the selected bus. ? when the bsdtxo bit is set, logic 1 for an rtxinha or rtxinhb bit in a rt confguration register (or a bus shutdown mode command with auto shutdown enabled) inhibits transmit only on the selected bus; but receive functions are unaffected. valid commands are heeded, but the rt transmits no responses. not recommended . the hi-613x rt1 and rt2 automatically fulfll unconditional mc4 bus shutdown in accordance with the bsdtxo setting, as well as mc5 override bus shutdown. the autobsd bit in the rt confguration register determines whether conditional mc20 selected bus shutdown and mc21 override selected bus shutdown are fulflled automatically, or by host writes to the rtxinha or rtxinhb bits in the appropriate rt confguration register: ? when the autobsd bit is logic 0 in the rt1 or rt2 confguration register, dxwrpdwlf ixooophqw lv glvdeohg for mc20 selected bus shutdown and mc21 override selected bus shutdown mode commands. the host fulflls bus shutdown and override by writing the rtxinha and rtxinhb bits in the appropriate rt confguration register. ? when the autobsd bit is logic 1 in the rt1 or rt2 confguration register, dxwrpdwlf ixooophqw lv hqdeohg for mc20 selected bus shutdown and mc21 override selected bus shutdown mode commands. when the received mode data word matches the value stored in the rt bus a (or b) select register, the rt automatically fulflls mc20 selected bus shutdown in accordance with the bsdtxo setting, as well as mc21 override selected bus shutdown. auto-shutdown bypasses the rtxinha and rtxinhb bits in the rt confguration register, but the upper 4 bits in the rts bit word register indicate tx and rx bus shutdown status. 2 intsel r/w 0 irq output type select. when this bit is 0, the irq (interrupt request) output generates a 1s negative pulse when enabled interrupt events occur. when this bit is logic 1, the irq output consists of a continuous low level output requiring host action to negate irq to the high state. when level interrupts are enabled, the host negates irq by asserting the ackirq input pin for at least 250ns. HI-6130, hi-6131
holt integrated circuits 33 bit no. mnemonic r/w reset function 1 imta r/w 0 indicate mt activity. when this bit equals 0, the active status output is not asserted for bus monitor activity, unless the monitored message involves another on- chip terminal). when this bit equals 1, enabled bus monitor activity is logically-ored with the activity of the other on-chip devices to determine active status; the active output is asserted during such bus monitor activity, whether or not the monitored message involves another on-chip terminal. 0 reserved - - this bit is not used and reads logic 0. 9.2. master status and reset register (0x0001) rt1reset rt2reset autoen ready bcmip bcactive mtpip mtmip rt2inh rt1inh mtreset 0 15 14 13 12 11 10 host access 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ramif rt1mip rt1mip r reserved 0 eecke r mr reset rw bit 9 8 7 6 5 4 3 2 1 0 this 16-bit register has a combination of read only and read-write bits. this register is cleared after mr pin master reset, but is unaffected by assertion of mtreset, rt1reset or rt2reset register bits. bit no. mnemonic r/w reset function 15 ready r 0 7kh5(HI-6130, hi-6131
holt integrated circuits 34 bit no. mnemonic r/w reset function 11 rt2reset r/w 0 remote terminal 2 reset. when written to logic 1, this bit initiates rt2 reset by clearing the stex start execution bit in the rt2 confguration register, then performing the rt soft reset actions described in section 23 . this bit remains high until reset is complete. while this bit remains high, the ready output pin and register bit 15 are held low, host ram and register access is suspended. while ready = 0, any host read access returns the value in this register, regardless of address provided. upon reset completion, this bit self-clears to logic 0, the ready pin goes high and host read/ write access is restored. 10 rt1reset r/w 0 remote terminal 1 reset. when written to logic 1, this bit initiates rt1 reset by clearing the stex start execution bit in the rt1 confguration register, then performing the rt soft reset actions described in section 23 . this bit remains high until reset is complete. while this bit remains high, the ready output pin and register bit 15 are held low, host ram and register access is suspended. while ready = 0, any host read access returns the value in this register, regardless of address provided. upon reset completion, this bit self-clears to logic 0, the ready pin goes high and host read/ write access is restored. 9 bcmip r 0 bc message in process. this bit is high when the bc is processing a mil-std-1553 message. falling edge occurs at message completion, after register and ram buffer updates. 8 bcactive r 0 bc active. this bit is high when the bc is enabled and running. it will read logic 1 during mil-std-1553 message processing and during programmed delays. 7 mtmip r 0 bus monitor message in process. this bit is set when a valid mil-std-1553 command is decoded, and is reset upon monitored message completion. 6 mtpip r 0 bus monitor packet in process. this bit is set at start of a data packet and is reset when the packet is deemed complete. 5 rt2mip r 0 remote terminal 2 message in process. this bit is set when a valid mil-std-1553 command is decoded for rt2, and is reset upon message completion. 4 rt1mip r 0 remote terminal 1 message in process. this bit is set when a valid mil-std-1553 command is decoded for rt1, and is reset upon message completion. HI-6130, hi-6131
holt integrated circuits 35 bit no. mnemonic r/w reset function 3 rt2inh r 0 remote terminal 2 bus inhibited. this bit is high when one bus is inhibited for rt2 due to execution of a bus shutdown mode code command. the shut-down bus is identifed in the rt2 bit (built-in test) word register. shut-down can be ended by bus shutdown override mode code command, mr reset or setting the rt2reset bit in this register. 2 rt1inh r 0 remote terminal 1 bus inhibited. this bit is high when one bus is inhibited for rt1 due to execution of a bus shutdown mode code command. the shut-down bus is identifed in the rt1 bit (built-in test) word register. shut-down can be ended by bus shutdown override mode code command, mr reset or setting the rt1reset bit in this register. 1 eecke r 0 eeprom checksum error. this function only applies when the autoen input pin is logic 1 at rising edge of mr master reset. this enables auto-initialization from serial eeprom, as well as rt or mt soft reset with auto-initialization. the eecke bit is set (as well as bit 14 in the hardware pending interrupt register, 0x0006) when a serial eeprom checksum failure occurs. such failure may occur during full auto-initialization after mr master reset, or during execution of a partial, terminal-specifc reset after assertion of the rt1reset, rt2reset or mtreset bits in this register. 0 ramif r 0 ram initialization fail interrupt. this function only applies when the autoen input pin is logic 1 at rising edge of mr master reset. this enables auto-initialization from serial eeprom, as well as terminal-specifc partial auto-initialization during rt or mt soft reset. the ramif bit is set (as well as bit 13 in the hardware pending interrupt register, 0x0006) when one or more initialized ram locations do not match their two corresponding serial eeprom byte locations. such failure may occur during full auto-initialization after mr master reset, or during execution of a partial, terminal-specifc reset after assertion of the rt1reset, rt2reset or mtreset bits in this register. HI-6130, hi-6131
holt integrated circuits 36 9.3. overview of interrupts for interrupt management, the host accesses up to thirteen hi-613x registers and a 64-word circular interrupt log buffer in ram. the log buffer and the interrupt count & log address register are utilized in any system design involving interrupts. in addition, there are four 3-register groups, identifed by terminal function. one 3-register group is for hardware interrupts; this register triplet is active in every hi-613x design. other 3-register groups are only active when the corresponding terminal functions are enabled; these are the interrupt register triplets used for bus controller, bus monitor and remote terminal interrupts. the remote terminal interrupt register triplet is shared by rt1 and rt2. each interrupt register triplet for bc, smt or imt, rt or hardware consists of ? an interrupt enable register to enable and disable interrupt recognition ? a pending interrupt register to capture the occurrence of enabled interrupts ? an interrupt output enable register selectively enables irq output to host when enabled interrupts occur within each register triplet, corresponding register bits are mapped to the same interrupt-causing event. initialize the interrupt enable register to select interrupt-causing events heeded by the hi-613x; most applications utilize just a subset of the available interrupt options. interrupt-causing events are ignored if their corresponding bits are reset in the interrupt enable register. setting an interrupt enable register bit from 0 to 1 does not trigger interrupt recognition for events that occurred while the bit was zero. the next datasheet sections describes interrupt features active in all hi-613x projects, namely the interrupt log buffer, the interrupt count & log address register and the hardware interrupt register triplet. 9.4. hardware interrupt behavior behavior described here for hardware interrupts closely resembles the behavior for the bc, rt and smt or imt interrupt register triplets, described later in the four corresponding sections of this datasheet. when an enabled hardware interrupt event occurs, the interrupt log buffer is updated and a bit is set in the hardware pending interrupt register. this action takes place only if the bit for the interrupt-causing event was already set in the hardware interrupt enable register. the host can poll the hardware pending interrupt register to detect occurrence of hardware interrupts, indicated by non-zero value. when the host reads the hardware pending interrupt register, it automatically clears to 0x0000. when an enabled hardware interrupt event occurs, if the corresponding bit is also set in the hardware interrupt output enable register, the irq output is asserted to alert the host. thus, the hardware interrupt output enable register establishes two interrupt priority levels for hardware events: high priority interrupts generate an irq signal output, while low priority interrupts do not. the host detects low priority interrupts by polling the hardware pending interrupt register. a single irq host interrupt output signal is shared by all enabled interrupt conditions having bits set in the hardware, bc, rt or mt interrupt output enable registers. multiple interrupt-causing events can occur simultaneously, so each irq output assertion can result from one or more interrupt conditions. when the host receives an irq signal from the device, it identifes the event (or events) that triggered the interrupt. the host has two options: (a) go to the interrupt log buffer (using the method described in sections 9.5 and 9.6), or (b) use a hardware-assisted scheme using the three low order bits in the hardware pending interrupt register to identify new interrupt(s). for the second method, the host reads the hardware pending interrupt register. while bits 15-3 in this register identify hardware interrupt conditions, the three low-order register bits indicate zero vs. non-zero status for the bc, rt and mt pending interrupt registers. if any of these bits is logic 1, the corresponding pending interrupt register has one or more interrupt fags set. any combination of these three bits may be set, or all three bits may be zero, if only hardware interrupt(s) occurred. when the host reads any of the four pending interrupt registers, the read access self-resets the register to 0x0000. thus, the host should retain the read value from the hardware pending interrupt register when HI-6130, hi-6131
holt integrated circuits 37 1 or more bits are non-zero in the bit 2-0 range. these bits indicate zero vs. non-zero status for the bc, rt and mt pending interrupt registers: ? when bits 2-0 in the hardware pending interrupt register read 000, there are no new interrupts in the bc, rt and mt pending interrupt registers. ? when bcip (bc interrupt pending) bit 0 is set in the hardware pending interrupt register, the bc pending in - terrupt register contains a nonzero value. the host can read the bc pending interrupt register to identify the specifc bus controller interrupt event(s). ? when mtip (mt interrupt pending) bit 1 is set in the hardware pending interrupt register, the mt pending inter - rupt register contains a nonzero value. the host can read the mt pending interrupt register (shared by smt or imt) to identify the specifc bus monitor interrupt event(s). ? when rtip (rt interrupt pending) bit 1 is set in the hardware pending interrupt register, the rt pending inter - rupt register contains a nonzero value. the host can read the rt pending interrupt register to identify specifc rt1 or rt2 interrupt event(s). when polling the pending interrupt registers to identify low priority interrupts that do not assert the irq output, the same decoding method can be applied. a single read of the hardware pending interrupt register reveals zero vs. non-zero status of all four pending interrupt registers. alternately, the host can poll the interrupt count & log address register to identify low priority interrupts that do not assert the irq output. bits 15:9 in this register contain a 7-bit count value indicating the number of interrupts logged (0 - 127) since the interrupt count & log address register was last read. although the interrupt log buffer only holds data from the last 32 interrupts, register bits 15:9 count beyond 32 for buffer overrun detection. counting stops at 127. register bits 15:9 are reset automatically when the host reads the interrupt count & log address register. 9.5. ,qwhuuxsw&rxqw/rjgguhvv5hjlvwhu msb 0 0 1 0 0 0 0 0 0 0 0 0 0 0 r 0 1 interrupt log address msb interrupt count mr reset host access bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 this 16-bit register is read-only and is fully maintained by hi-613x logic. the register contains 0x0180 after mr pin master reset. it is not affected by assertion of mtreset, rt1reset or rt2reset bits in the master status and reset register (0x0001). the value in interrupt log address register bits 8:0 is a 9-bit address pointer to the circular 64-word interrupt log buffer, located in ram. register bits 8:6 are always 1-1-0 so the 9-bit address pointer ranges from 0x0180 to 0x019e. this pointer indicates the storage address for two information words that will be stored for the next-occurring interrupt. the value is always even since two words are stored for each interrupt. upper register bits 15:9 contain a 7-bit count value for the number of interrupts logged (0 - 127) since the interrupt count & log address register was last read. although the circular interrupt log buffer only retains data from the last 32 interrupts, counting continues beyond 32 so the host can detect circular buffer overrun. bits 15:9 stop incrementing at full count (127 interrupts) and automatically reset to zero when the host reads this register. after mr master reset, the hi-613x initializes this register to 0x0180, an interrupt count of zero and interrupt log buffer address of 0x180. after reset, the frst interrupt stores words at buffer addresses 0x0180 and 0x0181. subsequent interrupts store word pairs at sequential addresses. information words for the 32nd interrupt are stored in last two buffer addresses 0x01be and 0x01bf, and the interrupt log address rolls over to read 0x0180, where interrupt information for the 33rd post-reset interrupt will be stored. HI-6130, hi-6131
holt integrated circuits 38 9.6. interrupt log buffer shown in figure 15, the interrupt log buffer is a circular 64-word buffer in ram, residing at address range 0x0180 to 0x01bf. device logic stores two information words in the buffer for each enabled interrupt that occurs, so buffer size dictates storage for up to 32 interrupt events. after the 32nd, 64th, 96th,... interrupt occurs, the buffer address pointer (bits 8:0 in register 0x000a) wraps around to buffer start address 0x0180 and subsequent interrupts overwrite previ - ously stored interrupt information. hi-613x interrupt logic stores two words in the interrupt log buffer for each enabled interrupt that occurs: an interrupt identifcation word and an interrupt address word. the interrupt identifcation word (iiw) identifes the occurring inter - rupt type using a word format identical to the applicable pending interrupt register. more than one bit may be asserted in an interrupt identifcation word. for example, ibr (interrupt broadcast received) and merr (interrupt message error) can occur for the same rt message. one assertion of the int output pin alerts the host when concurrent mes - sage interrupts occur. the log buffer interrupt address word varies, depending on the interrupt type. hardware interrupts are not directly linked with command or message processing. hardware interrupts write an interrupt address word value of 0x0000. for bc, smt or imt interrupts, the interrupt address word (iaw) identifes the message in which the interrupt oc - curred. for rt interrupts, the interrupt address word (iaw) identifes the command word for the message in which the interrupt occurred: interrupt type ,qwhuuxsw,ghqwlfdwlrq:rug,,: interrupt address word (iaw) hardware matches format of hardware pending interrupt register 0x0006 on page 40 always 0x0000 bus controller (bc) matches format of the bc pending interrupt register 0x0007 on page 90 a bc control/status block address, points to the block status word of the message in which interrupt occurred simple bus monitor (smt) matches the format of the smt pending interrupt register 0x0008 on page 111 an smt command buffer address, points to the block status word of the message in which interrupt occurred irig-106 bus monitor (imt) matches the format of the imt pending interrupt register 0x0008 on page 140 an imt integrated data buffer address, points to the block status word of the message in which interrupt occurred remote terminal rt1 and/or rt2 matches format of rt1 / rt2 pending interrupt register 0x0009 on page 158 rt1 or rt2 descriptor table address pointing to the command word of the message in which interrupt occurred for a given terminal (bc, smt, imt or rt1/rt2) multiple interrupts can be enabled, and two or more interrupts can occur in a single message. there will be a single 2-word log buffer update and the interrupt information word will have one bit set for each occurring interrupt. simultaneous interrupts for one terminal (having interrupt output enabled) are logically-ored, resulting in a single assertion of the irq output to the host. when operating with two or more enabled terminal devices (bc, smt, imt or rt1/rt2), simultaneous interrupts can occur in the same message for multiple terminals. each terminal device with occurring interrupt(s) will have its own 2-word log buffer update. simultaneous interrupts for multiple terminals (having interrupt output enabled) are logically-ored, resulting in a single assertion of the irq output to the host. in later data sheet sections, defnitions are provided for interrupt register triplets used by the bc (bus controller), smt (simple monitor terminal), imt (irig-106 monitor terminal) and rt (remote terminal). HI-6130, hi-6131
holt integrated circuits 39 interrupt log address register is initialized by device logi ct o point to this address after hardwarer eset (mr) or softwar er eset 0x0187 0x0186 0x0185 0x0184 0x0183 0x0182 0x0181 0x0180 0x018b 0x018a 0x0189 0x0188 0x01b7 0x01b6 0x01b5 0x01b4 0x01bf 0x01be 0x01bd 0x01bc 0x01bb 0x01ba 0x01b9 0x01b8 interrupt 1 interrupt 1 interrupt address w ord interrupt information w ord interrupt 2 interrupt 2 interrupt address w ord interrupt information w ord interrupt 3 interrupt 3 interrupt address w ord interrupt 4 interrupt address w ord interrupt information w ord interrupt 4 interrupt information w ord interrupt 5 interrupt 5 interrupt address w ord interrupt 6 interrupt address w ord interrupt information w ord interrupt 6 interrupt information w ord interrupt 30 interrupt 30 interrupt address w ord interrupt 29 interrupt address w ord interrupt information w ord interrupt 29 interrupt information w ord interrupt 28 interrupt 28 interrupt address w ord interrupt 27 interrupt address w ord interrupt information w ord interrupt 27 interrupt . . . . . . . . information w ord interrupt 31 interrupt 31 interrupt address w ord interrupt information w ord interrupt 32 interrupt 32 interrupt address w ord interrupt information w ord the interrupt log address register pointst ot his address afte ri nterrupt 31 event occurs. upon interrupt 32 completion, device logi cr einitializes th el og address pointer to 0x0180 beforei nterrupt 33 is processed. figure 3. fixed address mapping for interrupt log buffer HI-6130, hi-6131
holt integrated circuits 40 9.7. hardware interrupt registers 9.7.1. hardware interrupt enable register (0x000f) mtttro hspiint bcttro bcttm mtttm reserved lbfa 0 lbfb 0 0 0 0 0 0 1 0 rt2ttm rt1ttm rw 0 0 rt2apf rt1apf 1 1 r 0 * bits 4 - 0 are read-only and cannot be modified by host. 0 reserved reserved 1 ramif / uncre eecke / ramerr mr reset host access bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 9.7.2. hardware pending interrupt register (0x0006) mtttro hspiint bcttro bcttm mtttm rtip lbfa 0 lbfb 0 0 0 0 0 0 0 0 rt2ttm rt1ttm r 0 0 rt2apf rt1apf 0 0 r * 0 * bits 2 - 0 are set for pending interrupts from rt (rt1 or rt2), mt or bc 0 mtip bcip 0 ramif / uncre eecke / ramerr mr reset host access bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 9.7.3. hardware interrupt output enable register (0x0013) mtttro hspiint bcttro bcttm mtttm reserved lbfa 0 lbfb 0 0 0 0 0 0 1 0 rt2ttm rt1ttm rw 0 0 rt2apf rt1apf 1 1 r 0 * bits 2 - 0 are read-only and cannot be set by host. 0 reserved reserved 1 ramif / uncre eecke / ramerr mr reset host access bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 these three registers govern hardware interrupt behavior. as explained on the preceding page, bits 2-0 in the hardware pending interrupt register are set whenever interrupt bits are set in the other three pending interrupt registers (rt, 07dqg%&7khwdeohehorzuvwghvfulehvwkhfrpprqelwvlqdoowkuhhuhjlvwhuvdqgwkhqghvfulehvuhjlvwhu to-register differences for bits 2-0. bit no. mnemonic r/w reset function 15 hspiint r/w 0 host spi interrupt. this bit only applies to hi-6131 with spi host interface, which operates in spi slave mode. an unexpected number of sck clock pulses occured during a spi transaction. HI-6130, hi-6131
holt integrated circuits 41 bit no. mnemonic r/w reset function 14 eecke r/w 1 eeprom checksum error interrupt. this function only applies when the ramedc input pin is logic 0 and the autoen input pin is logic 1 at rising edge of mr master reset. this enables auto-initialization from serial eeprom, as well as rt or mt soft reset with auto-initialization. this bit is logic 1 in the hardware interrupt enable register and in the hardware interrupt output enable register after mr master reset. the eecke bit is set in the hardware pending interrupt register (as well as bit 1 in the master status and reset register, 0x0001) when a serial eeprom checksum failure occurs during auto initialization, or execution of a partial reset caused by assertion of the rt1reset, rt2reset or mtreset bits in the master status and reset register, 0x0001. register bit 14 has a secondary function when input pin ramedc is connected to logic 1. when the ramedc pin is high, the available ram address space is reduced from 32k words to 24k words, but error detection and correction (edc) is performed after every ram address read cycle. ramerr detected and corrected 24k ram error. this function only applies when the device ramedc input pin is connected high, confguring the device for 24k ram with edc enabled. single-bit errors are automatically corrected by the device, but multiple- bit errors are not correctable. when a single-bit ram data error is detected and corrected, register bit 14 is set to logic 1. the eecke bit 1 in register 0x0001 is also cleared. when bit 14 is asserted in the hardware pending interrupt register 0x0009, the host can distinguish an eecke interrupt from a ramerr interrupt by reading the master status and reset register 0x0001. eecke bit 1 in that register will be logic 1 for eecke interrupt, logic 0 for cramerr interrupt. HI-6130, hi-6131
holt integrated circuits 42 bit no. mnemonic r/w reset function 13 ramif r/w 1 ram initialization fail interrupt. this function only applies when the ramedc input pin is logic 0 and the autoen input pin is logic 1 at rising edge of mr master reset. this enables auto-initialization from serial eeprom, as well as rt or mt soft reset with auto-initialization. this bit is logic 1 in the hardware interrupt enable register and in the hardware interrupt output enable register after mr master reset. the ramif bit is set in the hardware pending interrupt register (as well as bit 0 in the master status and reset register, 0x0001) when one or more initialized ram locations do not match their two corresponding serial eeprom byte locations. such failure occurs during auto initialization, or execution of a partial reset caused by assertion of the rt1reset, rt2reset or mtreset bits in the master status and reset register, 0x0001. register bit 14 has a secondary function when input pin ramedc is connected to logic 1. when the ramedc pin is high, the available ram address space is reduced from 32k words to 24k words, but error detection and correction (edc) is performed after every ram address read cycle. uncre uncorrected 24k ram error. this function only applies when the device ramedc input pin is connected high, confguring the device for 24k ram with edc enabled. the device automatically corrects single-bit errors, but multiple-bit errors are not correctable. when an uncorrectable ram data error is detected, register bit 13 is set to logic 1. the ramif bit 1 in register 0x0001 is also cleared. when bit 13 is asserted in the hardware pending interrupt register 0x0009, the host can distinguish a ramif interrupt from a uncre interrupt by reading the master status and reset register 0x0001. ramif bit 1 in that register will be logic 1 for ramif interrupt, logic 0 for uncre interrupt. 12 11 lbfa lbfb r/w 0 loopback fail bus a interrupt (lbfa) loopback fail bus b interrupt (lbfb) for all transmitted words, the device checks mil-std-1553 word validity for the subsequently received/decoded word detected on the bus. this includes sync, encoding, bit count and parity checking. the last word in each message transmitted by the device is also checked for data matching. the lbfa bit is set each time loop-back detects an invalid or mismatched word on bus a. the lbfb bit is set each time loop-back detects an invalid or mismatched word on bus b. 10 mtttro r/w 0 mt time tag counter rollover. the bus monitor time tag counter rolled over from full count to zero. depending on options selected in the time tag confguration register, the mt time count may be either 16 or 48 bits. HI-6130, hi-6131
holt integrated circuits 43 bit no. mnemonic r/w reset function 9 bcttro r/w 0 bc time tag counter rollover. the bus controller time tag counter rolled over from full count to zero. depending on options selected in the time tag confguration register, the bc time count may be either 16 or 32 bits. 8 rt2ttm r/w 0 rt2 time tag match. the 16-bit remote terminal 2 time tag counter incremented to a count matching the contained value in the rt2 time tag reload / match register. 7 rt1ttm r/w 0 rt1 time tag match. the 16-bit remote terminal 1 time tag counter incremented to a count matching the contained value in the rt1 time tag reload / match register. 6 mtttm r/w 0 mt time tag match. the bus monitor time tag counter incremented to a count matching the contained value in the mt time tag match registers. 5 bcttm r/w 0 bc time tag match. the bus controller time tag counter incremented to a count matching the contained value in the bc time tag match register(s). 4 rt2apf r/w 1 rt2 terminal address parity fail interrupt. the remote terminal address and parity bits (latched into the rt2 operational status register at rising edge of mr ) do not exhibit odd par - ity (do not have an odd number of bits having logic 1 state). note: rt2 address parity is only checked if the rt2ena pin is logic 1 at rising edge of mr . 3 rt1apf r/w 1 rt1 terminal address parity fail interrupt. the remote terminal address and parity bits (latched into the rt1 operational status register at rising edge of mr ) do not exhibit odd parity (do not have an odd number of bits having logic 1 state). note: rt1 address parity is only checked if the rt1ena pin is logic 1 at rising edge of mr . for the hardware interrupt enable register and the hardware interrupt output enable register only 2 ? 0 reserved bits 2-0 cannot be written and read back 000. for the hardware pending interrupt register only 2 rtip r 0 rt interrupt pending. when this bit is high, one or more bits are set in the rt pending interrupt register. the host can read that register (0x0009) to determine the rt1 or rt2 interrupt event(s). 1 mtip r 0 mt interrupt pending. when this bit is high, one or more bits are set in the mt pending interrupt register. the host can read that register (0x0008) to determine the mt interrupt event(s). HI-6130, hi-6131
holt integrated circuits 44 bit no. mnemonic r/w reset function 0 bcip r 0 bc interrupt pending. when this bit is high, one or more bits are set in the bc pending interrupt register. the host can read that register (0x0007) to determine the bc interrupt event(s). 9.8. time tag counter confguration each device (rt1, rt2, bc or mt) has an independent time tag counter used for time-stamping messages. the two remote terminals rt1 and rt2 have independent 16-bit time tag counters because each rt needs independent frxqwuhvhwdqgvqfkurqldwlrqordglqj,qwkh7lph7dj&rxqwhu&rqjxudwlrq5hjlvwhuelwvvhohfwwkhforfn source for both of the rt1 and rt2 time tag counters. the same clock source is shared by the bus controller. the host controls the free-running rt1 and rt2 time tag counters using bit pairs 11-10 (rt2) or 9-8 (rt1) in the time tag &rxqwhu&rqjxudwlrq5hjlvwhu+huhlvdvxppdurikrvwlqlwldwhgrshudwlrqvlqyroylqjwkh57wlphwdjfrxqwhuv a. clearing the 16-bit rt1 or rt2 time tag count to 0x0000. b. copying the rt1 or rt2 tt16 time tag utility register value into the 16-bit rt1 or rt2 time tag counter. c. copying the current 16-bit rt1 or rt2 time tag count value into the rt1 or rt2 tt16 time tag utility register. the bus controller (bc) can operate using either a 16- or 32-bit time tag counter, selected using register bit 3, bctt32, lqwkh7lph7dj&rxqwhu&rqjxudwlrq5hjlvwhu7kh%&wlphwdjfrxqwhuforfnvrxufhlvvhohfwhgxvlqjuhjlvwhuelwv 2-0. this common clock source is shared by the bc, rt1 and rt2. bit pair 13-12 is used for clearing bc time tag counter, loading the counter with a 16- or 32-bit value contained in the bc time tag reload register, or writing the current 16- or 32-bit bc time tag counter value to the bcmt time tag utility register set (shared by the bc and mt.) the free-running bc time tag counter can be reset to zero, loaded with an arbitrary value, or the current count can be captured. in 32-bit time tag mode, the full count is captured by simultaneously loading two utility registers. writing bits lqwkh7lph7dj&rxqwhu&rqjxudwlrq5hjlvwhulqlwldwhvwkhvhrshudwlrqv+huhlvdvxppdurikrvwlqlwldwhg operations involving the bc time tag counter: a. clearing a 16- or 32-bit bc time tag count, whichever is enabled. b. when 16-bit bc time tag count is enabled, loading the 16-bit bc time tag counter with the 16-bit value contained in the bc tt16 time tag utility register capturing the current 16-bit bc time tag counter value to the bc tt16 time tag utility register c. when 32-bit bc time tag count is enabled, loading the 32-bit bc time tag counter with the 32-bit value contained in the bc tt32 time tag utility register pair capturing the current 32-bit bc time tag counter value to the bc tt32 time tag utility register pair 7kh exv prqlwru 07 fdq rshudwh xvlqj hlwkhu d ru elw wlph wdj frxqwhu vhohfwhg xvlqj 07 &rqjxudwlrq register bits 1-0. when using 16-bit resolution, one register is adequate for holding time tag values. when using 48-bit time tag count resolution, three 16-bit registers are needed for each stored time tag count. the mt time tag counter forfnvrxufhlvvhohfwhgxvlqjelwvlqwkh7lph7dj&rxqwhu&rqjxudwlrq5hjlvwhu7kh07wlphwdjforfn source is separate from the source shared by the bc, rt1 and rt2. the free-running mt time tag counter can be reset to zero, loaded with an arbitrary value, or the current count can be captured. in 48-bit time tag mode, the full count is captured by simultaneously loading three utility registers. writing elwvlqwkh7lph7dj&rxqwhu&rqjxudwlrq5hjlvwhulqlwldwhvwkhvhrshudwlrqv HI-6130, hi-6131
holt integrated circuits 45 here is a summary of host-initiated operations involving the mt time tag counter: a. clearing a 16- or 48-bit mt time tag count, whichever is enabled. b. when 16-bit mt time tag count is enabled, ? loading the 16-bit mt time tag counter with the 16-bit value contained in the mt tt16 time tag utility register ? capturing the current 16-bit mt time tag counter value to the mt tt16 time tag utility register c. when 48-bit mt time tag count is enabled, ? loading the 48-bit mt time tag counter with the 48-bit value contained in the mt tt48 time tag utility register triplet ? capturing the current 48-bit mt time tag counter value to the mt tt48 time tag utility register triplet when 48-bit mt time tag count is enabled host interrupts can be generated when any of the four time tag counters in the device reach preset values contained in time tag match registers. refer to the section 9.3 . 9.9. 7lph7dj&rxqwhu&rqjxudwlrq5hjlvwhu bctta1 mttta1 rt1tta0 rt1tta1 rt1tta0 rt1tta1 mttck2 mttck3 bctt32 ttck2 bctta0 ttck0 mttck1 mttck0 mttta0 ttck1 rw mr reset host access bit 15 14 13 12 11 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 8 7 6 5 4 3 2 1 0 this 16-bit read-write register is cleared after mr pin master reset, but is unaffected by assertion of mtreset, rt1reset or rt2reset register bits. when written, register bits 15-8 work in pairs to initiate a particular action, such as clearing or loading one of these counters. when written, register bits 15-8 self reset to zero after initiating the assigned action. thus, bits 15-8 always read logic 0. register bits 7-0 are used for confguring the various time tag counters in the hi-613x device. these bits will read back the last value written by the host. HI-6130, hi-6131
holt integrated circuits 46 bit no. mnemonic r/w reset function 15 14 mttta1 mttta0 r/w 0 mt time tag action bits 1-0. after performing the action below, these host-written bits self reset to 00: bits 15-14 action 00 do nothing. 01 reset 16- or 48-bit mt time tag count to zero. 10 load the 16- or 48-bit value from bcmt time tag utility register(s) into the mt time tag count register(s). 11 capture current 16- or 48-bit value in the mt time tag count register(s) into the bcmt time tag utility register(s). if the mt is using 16-bit time tag, the mt time tag counter uses a single register address, 0x003a. the bcmt time tag utility register used for the load and capture operations is register address 0x003d. if the mt is using 48-bit time tag, the mt time tag counter uses three register addresses. the high-mid-low words are found at 0x003c, 0x003b and 0x003a. the triplet of bcmt time tag utility registers used for the load and capture operations is located at register addresses 0x003f (high), 0x003e (mid) and 0x003d (low). bit no. mnemonic r/w reset function 15 14 mttta1 mttta0 (continued) r/w 0 bits 1-0 in the mt confguration register, 0x0029 select irig-106 monitor, imt (always 48-bit time tag counting), or simple monitor, smt, (choice of 16-bit or 48-bit time tag counting): mt confguration register, bits 1-0 mt operation time tag mode 00 or 10 imt (irig-106) monitor mode 48-bit time tag 01 smt (simple) monitor mode 16-bit time tag 11 smt (simple) monitor mode 48-bit time tag when the mt is operating in simple mode with 48-bit time tag, the recorded command buffer entry for each 1553 message has eight 16- bit words. when operating with 16-bit time tag, the recorded command buffer entry for each 1553 message has four 16-bit words. HI-6130, hi-6131
holt integrated circuits 47 bit no. mnemonic r/w reset function 13 12 bctta1 bctta0 r/w 0 bc time tag action bits 1-0. after performing the action below, these host-written bits self reset to 00: bits 13-12 action 00 or 11 do nothing. 01 reset 16- or 32-bit bc time tag count to zero. 10 load the 16- or 32-bit value from bcmt time tag utility register(s) into the bc time tag count register(s). if bctt32 register bit 3 equals 0, the bc is using 16-bit time tag. the bc time tag counter uses a single register address, 0x0043. the bcmt time tag utility register used for these operations is register address 0x003d. if bctt32 register bit 3 equals 1 the bc is using 32-bit time tagging, so the bc time tag counter requires two 16-bit register addresses. the high and low bc time tag counter words are found at 0x0044 and 0x0043. the pair of bcmt time tag utility registers used for timer operations is located at register addresses 0x003e (high word) and 0x003d (low word). 11 10 rt2tta1 rt2tta0 r/w 0 rt2 time tag action bits 1-0. after performing the rt2 time tag counter action below, these host- written bits self reset to 00: bits 11-10 action 00 or 11 do nothing. 01 reset 16-bit rt2 time tag count to zero. 10 load the 16-bit value from the rt2 time tag utility register(s) into the rt2 time tag counter. 9 8 rt1tta1 rt1tta0 r/w 0 rt1 time tag action bits 1-0. after performing the rt1 time tag counter action below, these host- written bits self reset to 00: bits 9-8 action 00 or 11 do nothing. 01 reset 16-bit rt1 time tag count to zero. 10 load the 16-bit value from the rt1 time tag utility register(s) into the rt1 time tag counter. HI-6130, hi-6131
holt integrated circuits 48 bit no. mnemonic r/w reset function 7 6 5 4 mttck3 mttck2 mttck1 mttck0 r/w 0 mt time tag clock selection bits 3-0. these three bits select the clock source for the bc, rt1 and rt2 time tag counters from the following options: bits 3-2-1-0 mt time tag counter clock source 0-0-0-0 0-0-0-1 0-0-1-0 0-0-1-1 0-1-0-0 0-1-0-1 0-1-1-0 0-1-1-1 1-x-x-x time tag counter disabled. external clock provided at the mttclk input pin. internally generated 2s clock. internally generated 4s clock. internally generated 8s clock. internally generated 16s clock. internally generated 32s clock. internally generated 64s clock. internally generated 100s clock. 3 bctt32 r/w 0 bc time tag 32-bit count enable. when the bctt32 bit equals 0, the bc time tag counter is 16 bits. when the bctt32 bit equals 1, the bc time tag counter is 32 bits. 2 1 0 ttck2 ttck1 ttck0 r/w 0 bc and rt time tag clock selection bits 2-0. these three bits select the clock source for the bc, rt1 and rt2 time tag counters from the following options: bits 2-1-0 time tag counter clock source 0-0-0 0-0-1 0-1-0 0-1-1 1-0-0 1-0-1 1-1-0 1-1-1 time tag counter disabled. external clock provided at ttclk input pin. internally generated 2s clock. internally generated 4s clock. internally generated 8s clock. internally generated 16s clock. internally generated 32s clock. internally generated 64s clock. HI-6130, hi-6131
holt integrated circuits 49 9.10. memory address pointer registers (hi-6131 only) this section only applies for the hi-6131 with spi host interface. it does not apply to the HI-6130 with parallel bus interface. the hi-6131 spi uses predefned 8-bit instruction op codes to perform a variety of predetermined actions. some op codes must be followed by two or more operand bytes, while other spi codes perform their desired action without additional operands. examples of self-contained spi op codes include the fast access op codes used for reading or writing registers at the low end of the address space. fast access op codes used for direct addressing contain embedded register addresses, but only work over a limited address range. ? spi reads to register addresses 0 through 0x000f (decimal 15) use an 8-bit op code of the form 0x00 + (reg_addr << 2) where reg_addr = 0 to 0xf before left-shifting two bits. ? spi writes to register addresses 0 through 0x003f (decimal 63) use an 8-bit op code of the form 0x80 + reg_addr where reg_addr equals 0 to 0x3f. the two fast access op codes use a dedicated memory address pointer to perform their duties without affecting val - ues contained in other memory address pointer registers. the fast access memory address pointer cannot be read by the host, but is written each time a fast access op code is processed. the hi-6131 uses a memory address pointer for spi reads to register addresses over 0x000f, or for spi writes to register addresses over 0x003f. for most spi read and write operations, the starting memory address for the requested operation is written to the memory address pointer (or map) before the op code (using the map) is invoked. in the case of a multiword data transfer involving a range of sequential addresses, the memory address pointer is initialized with the starting (lowest) address. after the spi transfers data from the frst address, the memory address pointer automatically increments to the next address. when read access occurs, the device prefetches the data stored at the next address to support the fastest possible data rates. as long as the chip select stays low (asserted) and the spi master continues to provide serial clocks, data read/write transfers for sequential addresses continue until the chip select is negated. please refer to section 25.2 , describing spi host access and the spi op codes used for data transfer. for fexibility in confguring the hi-6131device, four independent memory address pointers are available. these can be assigned in any manner that supports application requirements. for example: ? to simplify data access while supporting concurrent terminal devices (bc, mt, rt1 and rt2), some devices may need a dedicated memory address pointer (map) while other devices may be able to share a map. ? consider using a dedicated memory address pointer for interrupt service routines. many spi operations are mul - tiword transfers that utilize the memory address pointer auto-increment feature. if interrupts are enabled during multiword transfers, a dedicated memory address pointer for the interrupt service routine avoids corruption of the map used by the interrupted routine. residing in the lower register address space, the four memory address pointers can be read or written with a single 8-bit fast access op code (plus the desired 16-bit data value, when writing). just one of the four map registers is enabled at any time. each of the four memory address pointers has a dedicated 8-bit map select op code that enables it by writing the master confguration register. or the host can directly write the mapsel (memory address pointer select) bits 11-10 in the master confguration register to enable the desired map register. full descriptions of spi data transfer methods are provided later in this document. HI-6130, hi-6131
holt integrated circuits 50 the four memory address pointer registers are: map1 memory address pointer register 0x000b map2 memory address pointer register 0x000c map3 memory address pointer register 0x000d map4 memory address pointer register 0x000e rw mr reset host access bit 15 14 13 12 11 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 8 7 6 5 4 3 2 1 0 register value msb lsb these 16-bit registers are read-write and are fully maintained by the host. these registers are cleared after mr pin master reset, but are unaffected by assertion of rt1reset, rt2reset or mtreset bits in the master status and reset register (0x0001). each of these registers has a unique spi op code that reads the map value in the register, and another op code that writes a new map value into the register. see spi op code table. the host selects the active map register by writing the mapsel (memory address pointer select) bits 11-10 in the master confguration register (see section 9.1 ), or by using the four defned map select spi op codes, described in section 25.2 . the active map register contains the memory address used for spi read write access to registers and ram. please refer to section 25.2 for a full description of the interface and the spi instruction op codes. HI-6130, hi-6131
holt integrated circuits 51 10. bus controller ? configuration and operation the hi-613x can operate as an autonomous mil-std-1553 bus controller (bc), requiring minimal host processor support. all mil-std-1553b error-checking is automatically performed, including rt response time, manchester ii encoding, sync type, bit count, word parity, word count, responding rt address, and detection of the full range of pos - sible error conditions encountered during bc operation. the device implements all mil-std-1553b message formats. message format is confgurable on a message by message basis. each message is individually programmable for command type. individual messages can be programmed for automatic retries on either bus, and interrupt requests may be enabled or disabled. the hi-613x bus controller provides a fexible means for scheduling major and minor frames, allowing insertion of asynchronous messages during frame execution. upon error, individual messages can be programmed for one or two automatic retries, and the bc can switch buses before retry occurs. message data is separated from control and status data, to serve the needs for double buffering in ram and bulk data transfers. before bus controller operation can begin, the bcena input pin must be connected to logic 1 to allow bc operation. all bus controller operational registers (see section 11 ) must be properly confgured. the bc instruction list in ram must be initialized to defne message sequencing and conditional execution, and fnally the host must assert bcstrt bit 13 in the master confguration register 0x0000 to initiate execution of instruction list op codes. the following pages provide the necessary details for successful bus controller operation. figure 3 shows the registers and ram resources utilized by the bus controller. all bus controller registers are fully described in section 11 . initial control of bc message sequencing involves the bc instruction list pointer in register 0x0034. before bc execution begins, the instruction list starting address is copied from the bc instruction list start address register, 0x0033. once message sequencing is underway, the bc instruction list pointer in register 0x0034 is updated by the bc control logic. the bc instruction list in ram comprises a series of 2-word entries, an instruction op code followed by a parameter word. while processing messages, the bc control logic fetches and executes the instruction op code referenced by the bc instruction list pointer from the bc instruction list. the pointer parameter, referencing the frst word in the message control/status block, must have the form 0xhhh8 or 0xhhh0, where each h represents a hex character, 0-9 or a-f. if the individual message is rt-to-rt, the address must have the form 0xhhh0. each op code word in the bc instruction list has the format: bit 15 14 13 12 11 10 condition code x odd parity p op code field validation field 9 8 7 6 5 4 3 2 1 0 1 0 1 0 x x x x x x x x x 0 x bus controller execution stops immediately if the bc logic fetches an op code word having one or more of these error conditions: ? bit 15 contains even parity ? bits 14-10 contain an undefned op code ? validation feld bits 9-5 do not equal 01010 if enabled in the bc interrupt enable register 0x0010, a bctrap interrupt occurs when execution stops because of an illegal op code. HI-6130, hi-6131
holt integrated circuits 52 bc instruction list pointer reg 0x0034 hi-613x register space bc instruction list start address reg 0x0033 parameter op code bus controller instruction list in ram data word n data word(s) increasing memory address parameter (pointer) parameter command word * bc control word message control / status block in ram time to next msg data block pointer block status word rt status word 2nd rt status word time tag word tx command word loopback word rt-rt message only * rx command word if rt-rt message message data block in ram 6 unused addresses time tag bits 31-16 if bc uses 32-bit time base bc general purpose queue pointer reg 0x0038 gpq word 63 gpq word 63 bc gp queue in ram op code op code gpq words 1 - 62 data word 1 figure 4. bus controller message sequence structures 10.1. bus controller condition codes for most op codes, execution is conditional, depending on evaluation of the condition code feld. condition code bits 3-0 defne the specifc condition. condition code bit 4 identifes the required outcome for op code execution, true or false, following evaluation of condition code bits 3-0. the host has read-only access to the bc condition codes by reading the bc condition code register 0x0037. eight of the condition codes (1000 through 1111) are set or cleared based on the outcome of the most recent message. the remaining eight codes are general purpose condition codes, gp0 through gp7. three processes affect values of the general purpose condition code bits: (a) they may be toggled, set or cleared when the bc logic executes a flg (gp flags bits) op code. (b) they may be toggled, set or cleared when the host writes the bc general purpose flag register 0x0037. (c) only gp0 and gp1 may be set or cleared when the bc logic executes a cmt (compare mes - sage timer) op code, or a cft (compare frame timer) op code. the sixteen bc condition codes are summarized in table 6 . HI-6130, hi-6131
holt integrated circuits 53 table 6. bus controller condition code table code bit 3-0 condition code bit 4 = 0 inverse bit 4 = 1 function 0x0 lt / gp0 gt-eq / gp0 less than or gp0 flag. this fag may be toggled, set or cleared when the bc logic executes a flg (general purpose flags bits) op code, or when the host writes the bc general purpose flag register 0x0037. this fag is also set or cleared based on the evaluation of a cmt (compare message timer) or cft (compare frame timer) instruction op code: lt / gp0 = 1 gt-eq / gp0 = 0 if cmt parameter < bc time to next message reg if cft parameter < bc frame time remaining reg lt / gp0 = 0 gt-eq / gp0 = 1 if cmt parameter = bc time to next message reg if cft parameter = bc frame time remaining reg lt / gp0 = 0 gt-eq / gp0 = 1 if cmt parameter > bc time to next message reg if cft parameter > bc frame time remaining reg lt / gp0 = 1 or 0 based on compared values gt-eq / gp0 = 0 or 1 based on compared values if cmt parameter bc time to next message reg if cft parameter bc frame time remaining reg 0x1 eq / gp1 ne / gp1 equal to or gp1 flag. this fag may be toggled, set or cleared when the bc logic executes a flg (general purpose flags bits) op code, or when the host writes the bc general purpose flag register 0x0037. this fag is also set or cleared based on the evaluation of a cmt (compare message timer) or cft (compare frame timer) instruction op code: eq / gp1 = 0 ne / gp1 = 1 if cmt parameter < bc time to next message reg if cft parameter < bc frame time remaining reg eq / gp1 = 1 ne / gp1 = 0 if cmt parameter = bc time to next message reg if cft parameter = bc frame time remaining reg eq / gp1 = 0 ne / gp1 = 1 if cmt parameter > bc time to next message reg if cft parameter > bc frame time remaining reg eq / gp1 = 0 ne / gp1 = 1 if cmt parameter bc time to next message reg if cft parameter bc frame time remaining reg HI-6130, hi-6131
holt integrated circuits 54 code bit 3-0 condition code bit 4 = 0 inverse bit 4 = 1 function 0x2 gp2 gp2 general purpose flag bits 2-7. these fags may be toggled, set or cleared when the bc logic executes a flg (general purpose flags bits) op code, or when the host writes the bc general purpose flag register 0x0037. 0x3 gp3 gp3 0x4 gp4 gp4 0x5 gp5 gp5 0x6 gp6 gp6 0x7 gp7 gp7 0x8 noresp resp no response flag. this fag is set when an rt failed to respond to a command, or responded later than the bc no response timeout programmed using bits 15-14 in the bc confguration register 0x0032. 0x9 fmterr fmterr format error flag. this fag is set when the received response to the last message had one or more violations to mil-std-1553b validation criteria, including problems with sync, encoding, bit count, parity, or word count. this fag is also set when the received rt status word response from the last message contained an incorrect rt address feld. 0xa goodblock goodblock good data block transfer. refecting status for the last 1553 message, this fag is set after completion of error-free rt-to-bc transfers, rt-to-rt transfers, or transmit mode code commands with data. this fag is reset after invalid messages, or after completion of bc- to-rt transfers, receive mode code commands with data, or mode code commands without data. this fag may be used to determine when the transmit aspect of an rt-to-rt transfer is error-free. 0xb mskstatset mskstatset masked status set. refecting status for the last 1553 message, this fag is set when one or both of the following conditions occurred: ? in the message bc control word, at least one of the sta - tus mask bits 14-9 are logic 0, but the corresponding bit or bits are set in the received rt status word. when the reserved bits mask (message bc control word bit 9) is logic 0, this fag is set when any or all of the three reserved bits are set in the received rt status word. ? in the bc confguration register 0x0032, the bcr (broad - cast command received) mask enable bit 0 is logic 1. the mask broadcast bit 5 in the message bc control word is logic 0, and the bcr (broadcast command received) bit 4 is logic 1 in the received rt status word. HI-6130, hi-6131
holt integrated circuits 55 code bit 3-0 condition code bit 4 = 0 inverse bit 4 = 1 function 0xc badmsg goodmsg bad message. refecting status for the last 1553 message, the bad message fag is set for format error, no response error, or loopback error. see sections 24.2.6 through 24.2.8 . a status set condition has no effect on the bad message condition code. 0xd 1retry 1retry 1 retry. if condition code bits 3:0 = 0xd and bit 4 = 0, one or two message retries is indicated. if condition code bits 3:0 = 0xd and bit 4 = 1, zero message retries is indicated. 0xe 2retry undefned 2 retries. if condition code bits 3:0 = 0xe and bit 4 = 0, two message retries is indicated. condition code bits 3:0 = 0xe and bit 4 = 1 is undefned. 0xf always never always. the always bit is set (condition code bit 4 = 0) to designate an instruction op code as unconditional. the never bit is set (condition code bit 4 = 1) to designate an instruction op code as nop (no op). 10.2. bus controller instruction op codes in the bc instruction list, each op code word contains a 5-bit instruction feld that spans bits 14-10. the instruction op codes are described in table 7 . four instructions execute unconditionally, without evaluating the condition code test. for these instructions, the condition code feld is dont care. the four unconditional instruction op codes are: 1. cmt (compare message timer) 2. cft (compare frame timer) 3. flg (general purpose flag bits) 4. xqf (execute and flip) all other instruction op codes execute conditionally. they execute only if evaluation of the condition code tests true, logic 1. if the condition code feld tests false, the bc instruction list pointer skips to the next instruction op code in the bc instruction list. many instruction op codes utilize the following parameter word in the bc instruction list. depending on the op code, the parameter may be a ram address, a time value, an interrupt bit pattern, an argument that sets or clears general purpose flag bits, or an immediate value. for some op codes, the parameter word is not used and is therefore dont care. for an xeq (execute message) instruction, the parameter is a ram address pointer referencing the start of the message control/status block. HI-6130, hi-6131
holt integrated circuits 56 these instructions control program execution: halt, jump, subroutine call and subroutine return. subroutine calls can be nested 8 levels deep. if bc call stack overfow or underfow occurs, device logic generates a cstkerr (call stack pointer error) interrupt, if enabled. other host interrupts are generated under program control using the interrupt request instruction. in this case, a 4-bit user-defned interrupt code is written to the bc interrupt request bits 3-0 in the bc pending interrupt register. other instructions are formed various duties: set, reset or toggle general purpose flag bits; load the time tag counter; load the frame time counter; begin a new bc frame; wait for external trigger, then start a new bc frame; evaluate remaining frame time; or evaluate time to next message. table 7. bus controller instruction op codes name instruction op code parameter function xeq execute message conditional 0x01 ram address for message control/ status block if the condition code evaluates true, execute the message at the parameter-specifed message control status block address. otherwise (condition code evaluates false), continue execution at the next op code in the bc instruction list. at the start of xeq message execution, if the fourth word in the message control/status block is nonzero, it is copied to the bc time to next message register, and message timer begins decrementing. the bc message sequencer does not fetch the next instruction op code until the message timer reaches zero. regarding condition codes used with xeq: ? if using lt, gt-eq, eq and ne (which are only modifed by the device upon completion of cmt or cft op codes) the host must not change the value of the shared function gp0 or gp1 fag bit during execution of the contingent message. ? if using gp flag bit status (gp0 through gp7) to enable a message, host must not alter the tested gp flag bit during execution of a contingent message. ? the always and never condition codes may be used with xeq. the following condition codes must not be used with xeq: badmsg, retry1 or retry2, noresp, mskstatset, fmterr or goodblock. HI-6130, hi-6131
holt integrated circuits 57 name instruction op code parameter function xqg execute message and go conditional 0x16 ram address for message control/ status block if the condition code evaluates true, execute the message at the parameter-specifed message control status block address. otherwise (condition code evaluates false), continue execution at the next op code in the bc instruction list. regarding condition codes used with xqg: ? if using lt, gt-eq, eq and ne (which are only modifed by the device upon completion of cmt or cft op codes) the host must not change the value of the shared function gp0 or gp1 fag bit during execution of the contingent message. ? if using gp flag bit status (gp0 through gp7) to enable a message, host must not alter the tested gp flag bit during execution of a contingent message. ? the always and never condition codes may be used with xqg. the following condition codes must not be used with xqg: badmsg, retry1 or retry2, noresp, mskstatset, fmterr or goodblock. at the start of xqg message execution, if the fourth (time to next message) word in the message control/status block is nonzero, it is copied to the bc time to next message register 0x0036, and this message timer begins countdown. completion of an xqg message may occur while message timer countdown continues. unlike xeq, the xqg op code does not wait for the decrementing message timer to hit 0 before fetching the next instruction op code. as long as op codes following xqg do not execute a 1553 message, each op code is performed after fetch. upon reaching a following xeq, xqg, xqf or xfg execute-message instruction, transaction of its 1553 message does not begin until time to next message count reaches 0. thus, programmed 1553 message timing is maintained, while allowing execution of non-message instruction op codes. jmp jump conditional 0x02 ram address within the bc instruction list if the condition code evaluates true, jump to the parameter-specifed instruction op code in the bc instruction list. otherwise (condition code evaluates false), continue execution at the next op code in the bc instruction list. cal call subroutine conditional 0x03 ram address within the bc instruction list if the condition code evaluates true, push address of the next instruction op code onto the 8-level bc call stack, then jump to the parameter-specifed instruction op code in the bc instruction list. otherwise (condition code evaluates false), continue execution at the next op code in the bc instruction list. HI-6130, hi-6131
holt integrated circuits 58 name instruction op code parameter function rtn return from subroutine conditional 0x04 not used (dont care) if the condition code evaluates true, pop the top address from the bc call stack, then jump to the popped instruction op code address in the bc instruction list. otherwise (condition code evaluates false), continue execution at the next op code in the bc instruction list. irq interrupt request conditional 0x06 4-bit interrupt pattern, 0x000n if the condition code evaluates true, generate a host interrupt by writing the parameter-specifed 4-bit value n to bits 8-5 in the bc pending interrupt register. otherwise, continue execution at the next op code in the bc instruction list. note: no interrupt is generated if n = 0 hlt halt conditional 0x07 not used (dont care) if the condition code evaluates true, stop execution of the bc instruction list until a new bc start is issued by the host. otherwise (condition code evaluates false), continue execution at the next op code in the bc instruction list. dly delay conditional 0x08 delay time value (1 s per lsb resolution) if the condition code evaluates true, initiate a delay equal to the parameter-specifed value. otherwise (condition code evaluates false), continue execution at the next op code in the bc instruction list. if the time-to-next message counter is in use, the dly parameter has higher priority than the count for an unfnished message timer delay. wft wait until frame timer equals 0 conditional 0x09 not used (dont care) if the condition code evaluates true, stop bc instruction list execution until the bc frame time counter decrements to 0. otherwise (condition code evaluates false), continue execution at the next op code in the bc instruction list. cft compare to frame timer conditional 0x0a time value (100 s / lsb resolution) compare the parameter-specifed time value to the bc frame time remaining register 0x0035. set and clear lt and eq bits 1 and 0 in the bc general purpose flag register (section 11.7 ). cmt compare to message timer unconditional 0x0b time value (1 s per lsb resolution) compare the parameter-specifed time value to the bc time to next message register 0x0036. set and clear lt and eq bits 1 and 0 in the bc general purpose flag register (section 11.7 ). when cmt is preceded by an xeq or xqf instruction, the bc time to next message register 0x0036 value used for comparison is always 0x0000 because the message timer (initiated by xeq or xqf) decrements to zero before fetching the cmp instruction. in this case, a cmt with non-zero parameter word always sets gt-eq and ne and always resets lt and eq fags. when cmt is preceded by an xeq or xqf instruction, a cmt with parameter word 0x0000 always sets gt-eq and eq and always resets lt and ne fags. further, the cmt op code will never set lt and ne, while clearing gt-eq and eq fags. HI-6130, hi-6131
holt integrated circuits 59 name instruction op code parameter function ltt load time tag counter conditional 0x0d time value (resolution is programmed by bits 2-0 in the time tag counter confguration register 0x0039) if the condition code evaluates true, load the bc time tag count register 0x0043 with the parameter-specifed time value. this represents bits 15-0 when the bc operates with 32-bit time tag. otherwise (condition code evaluates false), continue execution at the next op code in the bc instruction list. read lth regarding ltt-lth sequences. lth load time tag counter high conditional lth only applies when 32-bit time base is enabled 0x18 time value (resolution is programmed by bits 2-0 in the time tag counter confguration register 0x0039) if the condition code evaluates true, load the bc time tag count high register 0x0044 with the parameter-specifed time value. this represents bits 31-16 when bc operates with 32-bit time tag. otherwise (condition code evaluates false), continue execution at the next op code in the bc instruction list. if lth immediately follows an ltt instruction, all 32 counter bits are loaded simultaneously. if lth is not preceded by an ltt instruction, time count bits 15-0 in 0x0043 will be cleared to 0x0000 when bits 31-16 are written to register 0x0044. this instruction is only allowed when bctt32 bit 3 is logic 1 in the time tag counter confguration register 0x0039, selecting 32-bit time base operation for the bc and rt(s). if bctt32 is logic 0, this instruction stops instruction list execution, and generates an illegal instruction bctrap interrupt, if enabled. lft load frame timer conditional 0x0e time value (100 s / lsb resolution) if the condition code evaluates true, load the bc frame time remaining register 0x0035 with the parameter- specifed time value. otherwise (condition code evaluates false), continue execution at the next op code in the bc instruction list. sft start frame timer conditional 0x0f not used (dont care) if the condition code evaluates true, start decrementing the bc frame time remaining register 0x0035. otherwise (condition code evaluates false), continue execution at the next op code in the bc instruction list. ptt push time tag count conditional 0x10 not used (dont care) if the condition code evaluates true, push the value in the bc time tag count register 0x0043 onto the bc general purpose queue. otherwise (condition code evaluates false), continue execution at the next op code in the bc instruction list. HI-6130, hi-6131
holt integrated circuits 60 name instruction op code parameter function pth push time tag count high conditional pth only applies when 32-bit time base is enabled 0x19 not used (dont care) if the condition code evaluates true, push the value in the bc time tag count high register 0x0044 onto the bc general purpose queue. this represents bits 31-16 when bc operates with 32-bit time tag. otherwise (condition code evaluates false), continue execution at the next op code in the bc instruction list. this instruction is only allowed when bctt32 bit 3 is logic 1 in the time tag counter confguration register 0x0039, selecting 32-bit time base operation for the bc and rt(s). if bctt32 is logic 0, this instruction stops instruction list execution, and generates an illegal instruction bctrap interrupt, if enabled. ptb push time tag count both conditional ptb only applies when 32-bit time base is enabled 0x1a not used (dont care) if the condition code evaluates true, push the value in the bc time tag count high register 0x0044 and then push the value in the bc time tag count (low) register 0x0043 onto the bc general purpose queue. (both words are fetched simultaneously but pushed serially.) otherwise (condition code evaluates false), continue execution at the next op code in the bc instruction list. this instruction is only allowed when bctt32 bit 3 is logic 1 in the time tag counter confguration register 0x0039, selecting 32-bit time base operation for the bc and rt(s). if bctt32 is logic 0, this instruction stops instruction list execution, and generates an illegal instruction bctrap interrupt, if enabled. pbs push block status word conditional 0x11 not used (dont care) if the condition code evaluates true, push the value of the block status word from the most recent message onto the bc general purpose queue. otherwise (condition code evaluates false), continue execution at the next op code in the bc instruction list. psi push immediate value conditional 0x12 immediate value if the condition code evaluates true, push the parameter- specifed immediate value onto the bc general purpose queue. otherwise (condition code evaluates false), continue execution at the next op code in the bc instruction list. psm push indirect conditional 0x13 memory address if the condition code evaluates true, push the value stored at the parameter-specifed address onto the bc general purpose queue. otherwise (condition code evaluates false), continue execution at the next op code in the bc instruction list. wtg wait for external trigger conditional 0x14 not used (dont care) if the condition code evaluates true, wait for a rising edge (logic 0 to 1 transition) on the bctrig pin before continuing execution at the next op code in the bc instruction list otherwise (condition code evaluates false), continue execution at the next op code in the bc instruction list. HI-6130, hi-6131
holt integrated circuits 61 name instruction op code parameter function xqf execute and flip unconditional 0x15 ram address for message control/ status block unconditionally execute the message at the parameter- specifed message control/status block address. at message completion , if the condition code evaluates true, then toggle bit 4 of the message control/status block address, and store the new message control/status block address as the updated value of the parameter following the xqf instruction op code. as a result, the next time this address in the bc instruction list is executed, the processed message control/ status block resides at the updated address (old address xor 0x0010) instead of the old address. otherwise (condition code evaluates false) the value of the message control/status block address parameter is not changed. at the start of xqf message execution, if the fourth word in the message control/status block is nonzero, it is copied to the bc time to next message register, and message timer begins decrementing. the bc message sequencer does not fetch the next instruction op code until this message timer reaches zero. xfg execute, flip and go unconditional 0x1a ram address for message control/ status block unconditionally execute the message at the parameter- specifed message control/status block address. at message completion , if the condition code evaluates true, then toggle bit 4 of the message control/status block address, and store the new message control/status block address as the updated value of the parameter following the xfg instruction op code. as a result, the next time this address in the bc instruction list is executed, the processed message control/ status block resides at the updated address (old address xor 0x0010) instead of the old address. otherwise (condition code evaluates false) the value of the message control/status block address parameter is not changed. at the start of xqg message execution, if the fourth (time to next message) word in the message control/status block is nonzero, it is copied to the bc time to next message register 0x0036, and this message timer begins countdown. completion of an xqg message may occur while message timer countdown continues. unlike xqf, the xfg op code does not wait for the decrementing message timer to hit 0 before fetching the next instruction op code. as long as op codes following xfg do not execute a 1553 message, each op code is performed after fetch. upon reaching a following xeq, xqg, xqf or xfg execute-message instruction, transaction of its 1553 message does not begin until time to next message count reaches 0. thus, programmed 1553 message timing is maintained, while allowing execution of non-message instruction op codes. HI-6130, hi-6131
holt integrated circuits 62 name instruction op code parameter function wmp write immediate value to wmi memory pointer conditional 0x1b immediate value if the condition code evaluates true, write the parameter- specifed immediate value to the dedicated wmi memory pointer (a register not accessible by the host). otherwise (condition code evaluates false), continue execution at the next op code in the bc instruction list. immediate value must exceed 0x4f or wmp instruction has no effect. after reset, the default wmi memory pointer value is 0x0050. wmi write immediate value to memory conditional 0x1c immediate value if the condition code evaluates true, write the parameter- specifed immediate value to 0x0050 or the memory address specifed by the last wmp instruction performed. otherwise (condition code evaluates false), continue execution at the next op code in the bc instruction list. dsz decrement ram specifed by memory address, skip the next instruction if zero conditional 0x1d memory address if the condition code evaluates true, the memory address specifed by the parameter word is decremented. if the new value is non-zero, the next instruction is executed. if the decremented value is zero, the next instruction is skipped. otherwise (condition code evaluates false), continue execution at the next op code in the bc instruction list. the primary purpose of dsz is n-iteration repeating execution loops. n is initialized with a wmi op code, and the instruction following dsz is a jmp to top-of-loop. flg general purpose flag bits unconditional 0x0c word value sets, clears or toggles general purpose flag bits the parameter word value is used to set, clear, or toggle the lower byte in the bc general purpose flag register 0x0037. the upper and lower bytes in the parameter word provide 2-bit arguments that modify each of the eight gp fag bits, as illustrated below. 76543210 gp7 l0 l1 l3 l2 l4 15 14 13 12 11 10 98 h2 h3 h4 h6 h5 h7 high byte: clear gp bits 7-0 low byte: set gp bits 7-0 gp0 h0 h1 l5 l6 l7 parameter word bit parameter word bit lx = hx = h-l bit combinations modify gp flag bits no change set gpx clear gpx toggle gpx 0 1 0 1 0 0 1 1 figure 5. bus controller flag operation HI-6130, hi-6131
holt integrated circuits 63 10.3. bus controller general purpose queue the hi-613x bc architecture includes a general purpose queue, a 64-word circular buffer which the bc can use to convey information to the external bc host. various bc instruction op codes push data values onto the queue, such as the block status word for the last message, time tag counter values, immediate data values, or values stored in specifc ram addresses. the bc general purpose queue pointer 0x0038 (see section 11.8 ) is initialized with the default starting address 0x00c0 after reset. the queue is relocatable, so the host may overwrite the default base address. updated by the bc logic each time a data word is pushed onto the queue, the pointer in register 0x0038 always points to the next storage address in the queue to be written. the address pointer rolls over every 64th word written. if the bcgpq bit 13 is logic 1 in the bc interrupt enable register, a bc interrupt is generated when the general purpose queue pointer rolls over from its ending address to its base address. 10.4. bus controller message control / status blocks in the bc instruction list, each occurrence of the execute message instructions, xeq, xqg, xqf and xfg, refer - ences a mil-std-1553b message. the op code word is followed by the parameter word, a memory pointer indicating the ram start address for a corresponding message control/status block. the pointer address indicates the frst word in the message control/status block, the bc control word. figure 6 illustrates this relationship. the hi-613x is fully compatible with all mil-std-1553b message formats. for most mil-std-1553 messages, the corresponding message control/status block contains 8 words: ? bc control word. this word contains fags that select message format, choose the active bus, enable message retry and end-of-message interrupt, indicate expected rt status word fags, etc. ? mil-std-1553 command word. when message is rt-to-rt, this is the receive command word. ? data address pointer. for subaddress commands and mode code commands with data, this word identifes the start address of the message data block in ram. for mode commands without data, this word is not used. ? time-to-next message. the time count loaded here begins decrementing at start of message. when value ex - ceeds message execution time, it paces delivery of the next message. ? time tag word. the current value of the internal time tag count is written to the time tag word at start-of-mes - sage and again at the end-of-message. when the bc uses a 16-bit time base, this location contains the complete time count. when the bc uses 32-bit time base, this word contains time bits 15-0 and block word 7 contains time bits 31-16 (instead of loopback word). ? block status word. this word contains various message result fags. ? loopback word, containing the last word transmitted by the bc (16-bit time base only) or time tag bits 31-16 (32-bit time base only) ? rt status word received. this is the transmit rt status word when message is rt-to-rt. when the message is rt-to-rt, the message control/status block contains 8 additional words: ? transmit command word. ? receive rt status word. ? six unused word locations, to maintain 8 or 16 words per message control/status block. figure 6 shows the range of message control/status block variations. selected words in the message control/status block are described next. HI-6130, hi-6131
holt integrated circuits 64 message control / status block for all messages except rt-to-rt message control / status block for rt-to-rt messages only message control / status block for all messages except rt-to-rt message control / status block for rt-to-rt messages only block status wo rd high time tag word high time tag word low time tag word bus controller configured for 16-bit time base bus controller configured for 32-bit time base command word bc control word time to next msg data block pointer command word bc control word time to next msg data block pointer block status word rt status word rt status word time tag word loopback word rx command word bc control word time to next msg data block pointer block status word tx rt status word time tag word rx command word bc control word time to next msg data block pointer block status word time tag word loopback word rx rt status word tx command word 6 unused addresses tx rt status word rx rt status word tx command word 6 unused addresses increasing memory address figure 6. structure of bus controller message control / status blocks in ram 10.4.1. bc control word mcodfmt rtrtfmt bcstfmt maskbcr usebusa eomint reserved selftst rw bsymask rsvmask memask rtryena ssysmask tfmask srqmask txttmc17 mr reset host access bit 15 14 13 12 11 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 8 7 6 5 4 3 2 1 0 the bc control word is the frst word in each message control / status block. the bc control word is not transmitted on the mil-std-1553 bus. this word is initialized and maintained by the host to specify message attributes: message format, which bus to use, bit masks for the received rt status word, enabling interrupt at end-of-message, and enabling self test: HI-6130, hi-6131
holt integrated circuits 65 bit no. mnemonic r/w reset function 15 txttmc17 r/w 0 transmit time tag for synchronize mode code command mc17. this option bit only applies when bc confguration register ttsynen bit 3 is logic 1. see page 26. this bit affects only the synchronize with data mode code command, (mode code 0x11 or decimal 17). ? if this control word bit is logic 0 ( or if bc confguration register ttsynen bit 3 is logic 0) the bc transmits the value contained in the message data block as the data word for a synchronize mode code command mc17. the transmitted word is fetched from the ram address referenced by the data address pointer. ? if this control word bit and bc confguration register ttsynen bit 3 are both logic 1, the synchronize mode data word value originates from the 16-bit bc time base counter (low order 16 bits when using the 32-bit bc time base option). ? if bc confguration register ettsyn bit 2 is also logic 1, the transmitted time tag data word is always an even value; the least signifcant bit is always 0. ? when ettsyn bit 2 is logic 0, the data word least signifcant bit may be 0 or 1. see page 26. the transmitted data value is saved in the message data block, at the address indicated by the data address pointer word. 14 memask r/w 0 message error bit mask. if this bc control word bit is logic 0 and the message error bit 10 is logic 1 in the received rt status word, a status set condition will result. if this bc control word bit is logic 1, the message error bit 10 in the received rt status word has no effect on the outcome for a status set condition. note: a status set condition results if one or more of these events occurs: ? one or more of the mask bits 14-9 in the bc control word is logic 0 and the corresponding bit is logic 1 in the received rt status word, ? the bcrme bit 0 is logic 1 in the bc confguration register 0x0032 and the maskbcr bit in the bc control word is logic 0 and the broadcast command received bit 4 is logic 1 in the rt status word ? the bcrme bit 0 is logic 0 in the bc confguration register 0x0032 and the maskbcr bit in the bc control word differs from the broadcast command received bit 4 in the rt status word ? the received rt status word contains an rt address feld different from the rt address feld in the transmitted command word 13 srqmask r/w 0 service request bit mask. if this bc control word bit is logic 0 and the service request bit 8 is logic 1 in the received rt status word, a status set condition will result. if this bc control word bit is logic 1, the service request bit 8 in the received rt status word has no effect on the outcome for a status set condition. see note at end of memask bit description above. HI-6130, hi-6131
holt integrated circuits 66 bit no. mnemonic r/w reset function 12 bsymask r/w 0 busy bit mask. if this bc control word bit is logic 0 and the busy bit 3 is logic 1 in the received rt status word, a status set condition will result. if this bc control word bit is logic 1, the busy bit 3 in the received rt status word has no effect on the outcome for a status set condition. see note at end of memask bit description above. 11 ssysmask r/w 0 subsystem flag bit mask. if this bc control word bit is logic 0 and the subsystem flag bit 2 is logic 1 in the received rt status word, a status set condition will result. if this bc control word bit is logic 1, the subsystem flag bit 2 in the received rt status word has no effect on the outcome for a status set condition. see note at end of memask bit description above. 10 tfmask r/w 0 terminal flag bit mask. if this bc control word bit is logic 0 and the terminal flag bit 0 is logic 1 in the received rt status word, a status set condition will result. if this bc control word bit is logic 1, the terminal flag bit 0 in the received rt status word has no effect on the outcome for a status set condition. see note at end of memask bit description above. 9 rsvmask r/w 0 reserved bits mask. if this bc control word bit is logic 0 and one or more of the three reserved bits 7-5 is logic 1 in the received rt status word, a status set condition will result. if this bc control word bit is logic 1, the three reserved bits 7-5 in the received rt status word have no effect on the outcome for a status set condition. see note at end of memask bit description above. 8 rtryena r/w 0 retry enabled. if this control word bit is logic 1 and bcre (bc retry enable) bit 12 is logic 1 in the bc confguration register 0x0032, the bc will retry a message if rt response timeout or format error occurs. if this control word bit is logic 1 and bcre (bc retry enable) bit 12 is logic 1 and bcrsb (bc retry if status word bits set) bit 8 is also logic 1 in the bc confguration register 0x0032, the bc will retry a message when a status set condition occurs. see note at end of memask bit 14 description above. 7 usebusa r/w 0 use bus a / use bus b . if this control word bit is logic 1, the bc transmits the command on bus a. if this control word bit is logic 0, the bc transmits the command on bus b. HI-6130, hi-6131
holt integrated circuits 67 bit no. mnemonic r/w reset function 6 selftst r/w 0 self-test message off-line. if this control word bit is logic 1, transmission of this message onto the 1553 bus is inhibited. instead the digitally-encoded command word is looped back into the receive decoder for the selected bus. this tests both the encoding and decoding signal paths. upon message completion, loop test fail bit 8 in the block status word indicates the self-test result. if bc is confgured for 16-bit time base, the received loopback w ord is stored in the message control/status block. if the bc is confgured for 32- bit time base, time tag bits 31-16 are stored in the loopback word location. see section 24.2.7. programmed bc-mode digital loopback testing (off- line) on page 232 . 5 maskbcr r/w 0 mask broadcast command received bit. if the bcrme bit 0 is logic 1 in the bc confguration register 0x0032, then this control word bit is a mask bit like bits 14-9, acting upon the bcr broadcast command received bit 4 in the received rt status word: ? if this maskbcr control word bit is logic 0 and the broadcast command received bit 4 is logic 1 in the received rt status word, a status set condition will result. ? if this maskbcr control word bit is logic 1, the broadcast command received bit 4 in the received rt status word has no effect on the outcome for a status set condition. if the bcrme bit 0 is logic 0 in the bc confguration register 0x0032, then this maskbcr control word bit refects the expected state of the broadcast command received bit 4 in the received rt status word: ? if this maskbcr control word bit does not match the logic state of the broadcast command received bit 4 in the received rt status word, a status set condition will result. ? if this maskbcr control word bit matches the logic state of the broadcast command received bit 4 in the received rt status word, then the broadcast command received bit 4 in the received rt status word has no effect on the outcome for a status set condition. see table 8 . 4 eomint r/w 0 end of message interrupt. if the bceom bit 3 is logic 1 in the bc interrupt enable register 0x0010, an eom interrupt will occur upon message completion, if this control word bit is logic 1. 3 reserved r/w 0 this bit is not used. HI-6130, hi-6131
holt integrated circuits 68 bit no. mnemonic r/w reset function 2 1 0 mcodfmt bcstfmt rtrtfmt r/w 0 mode code message format. broadcast message format. rt to rt message format. the combination of these three message format bits selects the mil-std- 1553b message type: mode code bit 2 broadcast bit 1 rt-rt bit 0 message type 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 bc-to-rt if the t/ r bit * equals logic 0 rt-to-bc if the t/ r bit * equals logic 1 rt-to-rt broadcast bc-to-rt broadcast rt-to-rt mode code command do not use broadcast mode code command do not use * transmit / receive bit in command word note: bit 0 must be logic 1 for rt-rt messages. this is the single control point enabling the 16-word control block that confgures rt-rt messages. 10.4.2. time to next message word the hi-613x bus controller provides a programmable delay for time to next message. this word in the message control / status block specifes the delay from the start of this message, to the start of the next message. the delay is programmable with 1 s per lsb resolution, and has a maximum value of 65.535 milliseconds. when the specifed time to next message value is less than the actual time required to transact the current message, the next message starts immediately upon completion current message, after the minimum inter-message gap time of 4s. this gap corresponds to a bus dead time of 2s. 10.4.3. data block pointer the data block pointer in the message control / status block provides the starting address in ram for storage of message data words or mode code data. for bc-to-rt (receive) commands, this pointer contains the ram location for the frst data word transmitted by the bc. for rt-to-bc (transmit) commands or rt-to-rt commands, this pointer contains the ram location for storing the frst data word transmitted by the rt (and received by the bc). HI-6130, hi-6131
holt integrated circuits 69 10.4.4. bc block status word le iwe se mstatset gdb wag rtry1 rtry0 rw mbce tm som lbe statset fe bid eom mr reset host access bit 15 14 13 12 11 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 8 7 6 5 4 3 2 1 0 the block status word in the message control / status block provides information regarding message status (in- process or completed), the bus it was transmitted on, whether errors occurred during the message, and the type of occurring errors. this word is written into ram by the device after message completion. because it resides in ram, the host has read-write access, although this word is usually treated as read-only by the host. bit no. mnemonic r/w reset function 15 eom r/w 0 end of message. this bit is set upon completion of a bc message, whether or not errors occurred. when eom is set, the current value of the time tag word(s) is (are) written to the corresponding time tag word(s) in the bc message control/status block. 14 som r/w 0 start of message. this bit is set at the start of a bc message and cleared at the end of the message. when som is set (and reset), the current value of the time tag word(s) is (are) written to the corresponding time tag word(s) in the bc message control/status block. 13 bid r/w 0 bus id (bus b / bus a ). this bit is logic 1 if the bc message was transacted on bus b. this bit is logic 0 if the bc message was transacted on bus a. 12 mbce r/w 0 message block coding error. a programming test aid, this bit only applies when chkfmt bit 13 is logic 1 in the bc confguration register. each message bc control word has fags that indicate format: mode code command (bit 2), rt-rt message (bit 1) and broadcast message (bit 0). when chkfmt is 1, these fags are compared to the message command word(s) that follow the control word in the message block. when message format mismatch occurs (a bc programming error), this mbce bit is set in the message block status word. see chkfmt description in bc (bus controller) confguration register (0x0032) on page 73 . HI-6130, hi-6131
holt integrated circuits 70 bit no. mnemonic r/w reset function 11 statset r/w 0 status set. this bit is not affected by the values of mask bits 14-9 in the bc control word for the message. this bit is logic 1 when the received rt status word contains an unexpected bit value in the bit 10-0 range. the expected value is usually logic 0 for bits 10-0 in the received rt status word. exception: the expected value for broadcast command received bit 4 in the received rt status word is logic 1 when bcrme bit 0 is logic 1 in the bc confguration register 0x0032, and maskbcr bit in the bc control word bit is logic 0 10 fe r/w 0 format error. this bit is logic 1 when a received rt response violates mil-std-1553 message validation criteria. this includes sync, word count, encoding, bit count or parity errors. word bits 2-0 provide additional information. this fag is also set when the received rt status word response from the last message contained an incorrect rt address feld. 9 tm r/w 0 no response timeout error. this bit is logic 1 when an rt fails to respond, or responds later than the bc no response timeout interval specifed by bits 15-14 in the bc confguration register 0x0032. 8 lbe r/w 0 loopback error. the hi-613x bc evaluates its own 1553 message transmissions. the received version of each word transmitted by the bc is checked for 1553 validity (sync, encoding, bit count and/or parity error). in addition, for each message transacted, the received image for the last word transmitted by the bc is evaluated for data match. this bit is logic 1 when the received version for one or more words transmitted by the bc fails 1553 word validity criteria, and/or the received version for the last word transmitted by the bc does not match the manchester ii word transmitted by the bc. 7 mstatset r/w 0 masked status set. this bit is logic 1 when any of the following conditions occurs: ? one or more of the mask bits 14-9 in the bc control word is logic 0 and the corresponding bit is logic 1 in the received rt status word. ? or the bcrme bit 0 is logic 1 in the bc confguration register 0x0032 and the maskbcr bit in the bc control word is logic 0 and the broadcast command received bit 4 is logic 1 in the rt status word. ? or the bcrme bit 0 is logic 0 in the bc confguration register 0x0032 and the maskbcr bit in the bc control word differs from the broadcast command received bit 4 in the rt status word. ? or the received rt status word contains an rt address feld different from the rt address feld in the transmitted command word. HI-6130, hi-6131
holt integrated circuits 71 bit no. mnemonic r/w reset function 6 5 rtry1 rtry0 r/w 0 retry count 1 and retry count 0 if bcre (bc retry enable) bit 12 is logic 1 in the bc confguration register 0x0032 and rtryena bit 8 is logic 1 in the bc control word for this message, the bc will retry the message if rt response timeout or format error occurs. also, if bcre (bc retry enable) bit 12 is logic 1 and bcrsb (bc retry if status word bits set) bit 8 is logic 1 in the bc confguration register 0x0032 and rtryena bit 8 is logic 1 in the bc control word for this message, the bc will retry the message when a status set condition occurs. see mstatset bit 7 description above. the combination of these two bits indicates the number of times this message was retried: rtry1 bit 6 rtry0 bit 5 number of retries 0 0 1 1 0 1 0 1 0 1 2 not used 4 gdb r/w 0 good transmit data block transfer. this bit is set to logic 1 upon successful completion of an error-free rt-to- bc message, rt-to-rt message, or transmit mode code message with data. this bit always resets to logic 0 for any bc-to-rt message, mode code message without data, or any incomplete or invalid message. this bit may be used for determining when the transmit portion of an rt-to-rt message is error-free. if this bit and error flag bit 12 are both set to logic 1 in the block status word for an rt-to-rt message, the transmitting rt responded correctly but error occurred in the receiving rt portion of the message. 3 wag r/w 0 wrong rt address and/or no gap. this bit is logic 1 when one or both of the following conditions occur ? the rt address feld within a received rt status word does not match the rt address feld in the command word transmitted by the bc ? the bcgce bc gap check enable bit 1 in the bc confguration register 0x0032 and the rt responds with response time less than 4 s per mil-std-1553b, mid-parity bit to mid-sync, (2 s bus dead time). 2 le r/w 0 word count (length) error. this bit is logic 1 when an rt-to-bc message, rt-to-rt message, or transmit mode code message with data is transacted with the wrong number of data words. this bit always resets to logic 0 for bc-to-rt messages, receive mode code messages, or transmit mode code messages without data. 1 se r/w 0 sync error. this bit is logic 1 when an rt responds with data sync in its status word, or with command/status sync in a data word. HI-6130, hi-6131
holt integrated circuits 72 bit no. mnemonic r/w reset function 0 iwe r/w 0 invalid word error. this bit is logic 1 when an rt response in one or more words having at least one of the following errors: sync encoding error, manchester ii encoding error, bit count error, parity error. HI-6130, hi-6131
holt integrated circuits 73 11. bus controller register description in addition to the registers described here, a hi-6131 bus controller also utilizes one or more memory address pointer registers (described in section 9.10 ) for managing spi read/write operations. this comment does not apply for parallel bus interface HI-6130 designs. 11.1. bc (bus controller) confguration register (0x0032) chkfmt bcr1a bcto1 bcr2a mendv bcgte bsyndv ttsynen ettsyn bcre 0 bc2re 0 0 0 0 0 0 0 0 0 0 0 0 0 bcrme bcwdte rw bcto0 0 bcgce bcrsb 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mr reset host access bit no. mnemonic r/w reset function 15 ? 14 bcto1:0 r/w 0 bc time out select. this 2-bit feld selects the bc no response time-out delay from four available selections. excluding rt-rt commands, response delay is measured from command word mid-parity bit to status word mid-sync: bit 11:10 bus dead time time out (excludes rt-rt) 00 01 10 11 15s 20s 58s 138s 17s 22s 60s 140s for rt-rt commands, time out delay is measured per figure 8 in the rt validation test plan, sae as4111. that is, from mid-parity of the receive command to mid-sync of the frst received data word. this adds 42s for the embedded parity half-bit, transmit command word, transmit-rt status word and data half-sync within this interval: bit 11:10 txrt bus dead time rt-rt time out* 00 01 10 11 18s 23s 58s 138s 60s 65s 100s 180s *note: per rt validation test plan, fig. 8. all time out select values have C100ns / +500ns tolerance. HI-6130, hi-6131
holt integrated circuits 74 bit no. mnemonic r/w reset function 13 chkfmt r/w 0 check message format. when this bit equals logic 1, bc control word message format bits 2-0 (mode command, rt-rt message and broadcast fags) are compared to values for the message command word(s) that follow the control word in the message block. this is provided as a bc program development aid. when the chkfmt bit is logic 1 and message format mismatch occurs, the mbce message block coding error bit 12 is set in the message block status word (see section 10.4.4. bc block status word on page 69 ). if enabled, bc trap interrupt is generated (see section 11.15.3. bus controller (bc) interrupt output enable register (0x0014) on page 90 ). when the chkfmt bit is logic 0, no format checking occurs between bc control word bits 2-0 and the mil-std-1553 message command word(s). even with message format checking disabled, bc control word bit 0 must be logic 1 for rt-rt messages. this is the single control point enabling the 16-word bc control block that confgures an rt-to-rt message . 12 bcre r/w 0 bc retry enable. if bit 12 equals logic 0, command retries are disabled for all messages. if bit 12 equals logic 1, command retries can be enabled on an individual message basis by setting bit 8 in the bc control word for all messages to be retried. 11 bc2re r/w 0 bc second retry enable. if retries are enabled (register bit 12 equals 1) this bit selects the number of retries performed, if bit 11 equals logic 0, a single retry is performed. if bit 11 equals logic 1, up to two retries are performed. 10 bcr1a r/w 0 bc first retry use alternate bus. if retries are enabled (register bit 12 equals 1) this bit selects the bus used for the frst retry. if bit 10 equals 0, the frst retry is performed on the same bus from which the message was originally transmitted. if bit 10 equals 1, frst retry is performed on the alternate bus from which the message was originally transmitted. 9 bcr2a r/w 0 bc second retry use alternate bus. if frst and second retries are enabled (register bits 12:11 equal 1-1) this bit selects the bus used for the second retry. if bit 9 equals 0, the second retry is performed on the same bus where the message was originally transmitted. if bit 9 equals 1, second retry is performed on the alternate bus from where the message was originally transmitted. HI-6130, hi-6131
holt integrated circuits 75 bit no. mnemonic r/w reset function 8 bcrsb r/w 0 bc retry if unmasked status word bit set. this bit affects operation of bc retries. if bit 8 equals logic 0, the bc will not retry messages because of status bit(s) set in the rt status word, or status word with non-matching rt address feld. if retries are enabled and bit 8 equals logic 1, the bc will retry messages for these rt status word results: 1. one or more bc control word mask bits 14-9 is logic 0 (bits are not masked) and the corresponding bit is logic 1 in the received rt status word. 2. the bcr mask enable bit 0 equals 0 in the bc confguration register 0x0032. the broadcast command received (bcr) bit in the received rt status word differs from the mask bcr bit (bit 5) in the bc control word. 3. received status word rt address does not match command word rt address. 7 mendv r/w 0 message error status, no data is valid bit 7 affects bc validation of rt responses to transmit commands when the message error (me) bit is asserted in the received rt status word. when the mendv bit equals logic 0: ? when an rt responds message error status to a transmit command, the response is valid only if the status word is followed by the commanded number of data words. message result: condition block status word condition code register commanded number of data words good data block (gdb) bit = 1 good data block transfer (gdbt) bit = 1 if memask = 1 in bc control word masked status set (mstatset) bit = 1. masked status set (mstatset) bit = 1. status set (statset) bit = 1. ---------- HI-6130, hi-6131
holt integrated circuits 76 bit no. mnemonic r/w reset function 7 mendv (continued) r/w 0 ? if the rt responds message error status to a transmit command with the wrong number of data words or no data words, here is the message result: condition block status word condition code register wrong number of (or no) data words format error (fe) bit = 1 format error (fmterr) bit = 1 if memask = 1 in bc control word masked status set (mstatset) bit = 1. masked status set (mstatset) bit = 1. word count error (le) bit = 1. bad message (badmsg) bit = 1 status set (statset) bit = 1. ---------- when the mendv bit equals logic 1: ? when an rt responds message error status to a transmit command, the response is valid with the commanded number of data words, or me status with no data words. here is the message result: condition block status word condition code register commanded # of data words only, good data is not shown if no data good data block (gdb) bit = 1 good data block transfer (gdbt) bit = 1 if memask = 0 in bc control word masked status set (mstatset) bit = 1. masked status set (mstatset) bit = 1. status set (statset) bit = 1. ---------- HI-6130, hi-6131
holt integrated circuits 77 bit no. mnemonic r/w reset function 7 mendv (continued) r/w 0 ? if the rt responds message error status to a transmit command with the wrong number of data words (not 0), here is the message result: condition block status word condition code register wrong number of data words format error (fe) bit = 1 format error (fmterr) bit = 1 if memask = 0 in bc control word masked status set (mstatset) bit = 1. masked status set (mstatset) bit = 1. word count error (le) bit = 1. bad message (badmsg) bit = 1 status set (statset) bit = 1. ---------- the only 3 cases when an rt transmits message error status onto the bus: 1. an rt using illegal command detection receives an illegal command that otherwise meets all other validation requirements. the rt responds with status word only, with message error bit set. no data words are sent. 2. an rt receives a transmit status mode command (mc2). the previous valid command for the rt had message error status. the rt responds with status word only, with message error bit set. no data words are sent. 3. an rt receives a transmit last command mode command (mc18 decimal). the previous valid command for the rt set message error status. the rt responds with status word (with message error bit set) and one data word, the previous command word. in summary, message error status never occurs with more than one data word, and only occurs with one data word for the transmit last command mode code. besides illegal command detection, there is just one situation where message error status occurs, but status transmission is suppressed: the rt detects a valid receive command having correct rt address, but an invalid word is detected in the accompanying data words, or a gap occurs between words. in this situation, message error status is set but the rt suppresses its status word transmission. this suppressed me status is only seen by the bc if retrieved by a following transmit status or transmit last command mode command. HI-6130, hi-6131
holt integrated circuits 78 bit no. mnemonic r/w reset function 6 bsyndv r/w 0 busy status, no data, is valid bit 6 affects bc validation of rt responses to transmit commands when the busy bit is asserted in the received rt status word. when the bsndv bit equals logic 0: when an rt responds busy status to a transmit command, the response is valid only if the status word is followed by the commanded number of data words. here is the message result: condition block status word condition code register commanded number of data words good data block (gdb) bit = 1 good data block transfer (gdbt) bit = 1 if bsymask = 1 in bc control word masked status set (mstatset) bit = 1. masked status set (mstatset) bit = 1. status set (statset) bit = 1. ---------- ? if the rt responds busy status to a transmit command with the wrong number of data words or no data words, here is the message result: condition block status word condition code register wrong number of (or no) data words format error (fe) bit = 1 format error (fmterr) bit = 1 if bsymask = 1 in bc control word masked status set (mstatset) bit = 1. masked status set (mstatset) bit = 1. word count error (le) bit = 1. bad message (badmsg) bit = 1 status set (statset) bit = 1. ---------- when the bsndv bit equals logic 1: ? when an rt responds to a transmit command with busy status, the response is valid when accompanied by the commanded number of data words, or accompanied by no data words. here is the message result: condition block status word condition code register commanded # of data words only, good data is not shown if no data good data block (gdb) bit = 1 good data block transfer (gdbt) bit = 1 if bsymask = 0 in bc control word masked status set (mstatset) bit = 1. masked status set (mstatset) bit = 1. status set (statset) bit = 1. ---------- HI-6130, hi-6131
holt integrated circuits 79 bit no. mnemonic r/w reset function 6 bsyndv (continued) r/w 0 ? if the rt responds to a transmit command with busy status and the wrong number of data words (but not 0), here is the message result: condition block status word condition code register wrong number of data words format error (fe) bit = 1 format error (fmterr) bit = 1 if bsymask = 0 in bc control word masked status set (mstatset) bit = 1. masked status set (mstatset) bit = 1. word count error (le) bit = 1. bad message (badmsg) bit = 1 status set (statset) bit = 1. ---------- a busy rt is one that is functional, but cannot send or receive data when commanded by the bus controller. an rt that is busy sets the busy bit in its status word responses. in response to transmit commands, the busy terminal has no words to transmit, so only the status word is transmitted. in the case of the transmit vector word and transmit bit word mode code commands, even if the data is available to the terminal, it is prohibited to send the data word if the busy bit is set in the status word. there is just one defned situation in which an rt transmits busy status with one (and only one) data word: an rt receives a transmit last command mode command (mc18 decimal). when the previous valid command for the rt had busy status, the rt responds with last message status condition (with busy bit set) and one data word, the previous command word. 5 bcgte r/w 0 bc message gap timer enable. if bit 5 is logic 0, the bc does not add delay between 1553 messages. message timing is paced by the time required for the bc to complete message post processing. in this case, the minimum inter-message gap will be used, with a bus dead time of approximately 6 to 9s. if bit 5 is logic 1, the bc message timer is enabled. the time to next message value from the message control block is decremented at 1s rate. when the count decrements from 1 to 0, the next message starts. if the specifed message gap time is less than the time needed for the current message, the next message will start immediately after completion of the current message. in this case, the minimum inter- message gap will be used, with a bus dead time of approximately 6 to 9s. this allows the bc to implement minor frame cycle times without host processor intervention. HI-6130, hi-6131
holt integrated circuits 80 bit no. mnemonic r/w reset function 4 bcwdte r/w 0 bc watchdog timer (wdt) enabled. when this bit is logic 1, if the end of frame (eof) interrupt bit is set in the bc interrupt enable register, the bc sets the eof bit in the bc pending interrupt register when the bc frame timer decrements from 1 to 0. when using this feature, it is necessary to periodically reload the frame time register by means of the lft load frame time op code in the bc message sequence control block. the loaded value must allow for the worst-case frame time (including message retries). the wdt provides a failsafe recovery from faults such as message sequence stuck in repetitive loop without lft reload, or execution jumping to the wrong sequence. 3 ttsynen r/w 0 bc time tag synchronization enable this option bit only affects the synchronize with data mode code command, mc17. when this bit is logic 1, the source of the mode data issued with the synchronize mode command is determined by message bc control word txttmc17 bit 15 (see section 10.4.1 ) ? if bc control word txttmc17 bit 15 = logic 0, the synchronize mode data word originates from the message data block, at the ram address indicated by the data address pointer word. ? if bc control word txttmc17 bit 15 = logic 1, the synchronize mode data word value originates from the 16-bit bc time base counter (or the low order 16 bits, when using the 32-bit bc time base option). the transmitted data value is saved in the message data block, at the address indicated by the data address pointer word. if the ttsynen bit is logic 0, regardless of the state of message control word bit 15, the synchronize with data mode command (mc17) is always issued with mode data originating from the message data block, at the ram address indicated by the data address pointer word. 2 ettsyn r/w 0 even time tag sync. this bit only applies when ttsynen bit 3 is logic 1 and bc control word txttmc17 bit 15 is also logic 1, selecting synchronize mode data origin as time base counter. in this case, if ettsyn is logic 1, the transmitted time tag data word is always even; the low order bit is always 0. when the ettsyn bit is logic 0, the data word may be even or odd; the lsb may be 0 or 1. HI-6130, hi-6131
holt integrated circuits 81 bit no. mnemonic r/w reset function 1 bcgce r/w 0 bc gap check enable. when this bit is logic 1, the bc verifes that any transmission by a remote terminal on the bus is preceded by an inter-word gap of at least 4s. when this minimum gap time is violated, the bc declares the rt status word invalid, and the no gap error bit is set in the block status word. gap detection measures the time span from mid-parity of last received word, to mid-sync of the following word (defned here as detection of a properly encoded sync plus two bits). measured gap time is adjusted to evaluate just the interval of interest, corresponding to a bus dead time (end-of-parity to start-of-sync) of 2s minimum. when this bit is logic 0 (strongly recommended) the bc does not check for minimum bus dead time prior to start of transmission by a device on the mil-std-1553 bus. 0 bcrme r/w 0 bcr mask enable. this bit selects the function of bc control word bit 5, mask broadcast, when evaluating the bcr (broadcast command received) bit in rt status words. if bcr mask enable bit 0 is logic 1 , then rt status word bcr bit masking is enabled. the state of the mask bcr bit in each bc control word selectively allows or disallows bcr status testing by the bc: ? when mask bcr is logic 1 in a messages bc control word (dis - abling bcr status bit test), the value of the rt status word bcr bit is dont care in terms of affecting the occurrence of a status set condition. ? when mask bcr is logic 0 in the messages bc control word, status set occurs when the bcr bit in the received rt status word is logic 1. ? while broadcast commands never result in transmitted rt status, the mask bcr bit should be set in bc control words for transmit status or transmit last command mode commands immediately following broadcast messages. setting the mask bcr bit of the messages bc control word to logic 1 indicates the expected value of the bcr bit in the received rt status word. if bcr mask enable bit 0 is logic 0 , the mask bcr bit in a messages bc control word indicates the expected state of the bcr bit in the received rt status word. in this situation, whenever the bcr bit in the received rt status word differs from the state of the mask bcr bit in the bc control word, a status set condition occurs and the bc generates a status set interrupt, if enabled. table 8 summarizes the effects of bc confguration, message control word and rt status word on status set bit in the block status word. HI-6130, hi-6131
holt integrated circuits 82 table 8. effect of broadcast command received rt status bit on status set condition bc confguration register 0x0032 bcr mask enable bit 0 message control word mask bcr bit 5 received bcr bit 4 in the remote terminal status word resultant block status word status set bit 11 0 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 1 1 0 0 1 0 1 x 0 1 0 11.2. start address register for bus controller (bc) instruction list (0x0033) rw mr reset host access bit 15 14 13 12 11 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 8 7 6 5 4 3 2 1 0 register value msb lsb this 16-bit register is read-write and is fully maintained by the host. this register is cleared after mr pin master reset. this register is initialized with the base address of the re-locatable bc instruction list in device ram. 11.3. bus controller (bc) instruction list pointer (0x0034) r mr reset host access bit 15 14 13 12 11 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 8 7 6 5 4 3 2 1 0 register value msb lsb this 16-bit register is read-only and is fully maintained by the device. when the bus controller is enabled, setting bcstrt bit 13 in the master confguration register begins bus controller operation. the device copies the instruction list base address from register 0x0033 into this register. this pointer references pairs of words in the bc instruction list. each word pair is comprised of an op code word followed by a parameter word. pointer update occurs just before execution of the next bc instruction list op code, after execution of the prior op code, and evaluation of its result- dependent outcome. HI-6130, hi-6131
holt integrated circuits 83 11.4. bus controller (bc) frame time remaining register (0x0035) rw mr reset host access bit 15 14 13 12 11 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 8 7 6 5 4 3 2 1 0 register value msb lsb this 16-bit register is read-write. a value is written to this register upon execution of the bc instruction list op code, load frame timer (lft). time remaining value begins decrementing upon execution of the start frame timer (sft) instruction op code. the parameter word accompanying the op code word is the desired time value, expressed with a resolution of 100 s per lsb, with a maximum value of 6.5535 sec. 11.5. bus controller (bc) time to next message register (0x0036) r mr reset host access bit 15 14 13 12 11 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 8 7 6 5 4 3 2 1 0 register value msb lsb this 16-bit register is read-only. this programmable time-to-next message timer is loaded on a message-by-mes - sage basis, with values from word 4 in each message control / status block. the bc time-to-next message is defned as the time from the start of the current message to the start of the next message, i.e., mid-sync zero crossing to the next mid-sync zero crossing. this timer provides a 1 s per lsb resolution, with a maximum value of 65.535 ms. 11.6. bus controller (bc) condition code register (read 0x0037) retry1 mstatset bcrun gdbt fmterr gpf7 noresp gpf4 gpf3 retry0 badmsg r gpf6 gpf5 gpf2 lt / gp0 eq / gp1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mr reset host access sharing the same register address as the write-only general purpose flag register, this 16-bit register is read-only. bit 15 indicates bc run/stop status. with this exception, the upper 8 bits indicate results from the last message pro - cessed by the bus controller. the lower 8 bits of this register are general purpose fag bits, which may be set, cleared, or toggled by the host using the bc general purpose flag register (see page 33), or by the device by means of the general purpose flag bits (flg) instruction op code. further, bits 1-0 can be set or cleared by the device bc logic by execution of two bc instruction op codes: compare to frame timer (cft) and compare to message timer (cmt). HI-6130, hi-6131
holt integrated circuits 84 bit no. mnemonic r/w reset function 15 bc run r 0 bc run / stop this is a status bit, not a condition code. this bit indicates whether the bc is running or stopped. the bit is set to logic 1 when the bcstrt bit 13 in the master confguration register is asserted and the bcena input pin and bcena bit 12 in the master confguration register 0x0000 are both logic 1. once set, this bit resets to logic 0 if the bcena input pin or bcena register bit are reset to logic 0 by the host, or if the bc executes the hlt instruction, or if the bc executes an illegal op code. the illegal op code case will generate a bctrap interrupt, if enabled (see section 11.15.3. bus controller (bc) interrupt output enable register (0x0014) on page 90 ). 14 13 retry 1 retry 0 r 0 message retry status bits. bits 14-13 indicate the retry status of the most recent message the number of times message was retried: bit 14:13 number of message re-tries 0-0 0-1 1-0 1-1 0 1 2 not used 12 badmsg r 0 bad message. this bit is logic 1 to indicate message format error, loopback test failure, or no response error for the last message. 11 mstatset r 0 masked status set. this bit is set if one or more of the following conditions occurred during the last message: ? one or more of the status mask bits 14-9 are logic 0 in the bc control word, and the corresponding bits are logic 1 in the received rt status word. when bc control word reserved bits mask bit 9 is logic 0, this masked status set bit is set if any of the three reserved bits are set in the received rt status word. ? the bcr mask enable bit 0 is logic 0 in the bc confguration register 0x0032. opposite logic states occur for the mask bcr bit in the message bc control word and the broadcast command received (bcr) bit in the received rt status word. ? the bcr mask enable bit 0 is logic 1 in the bc confguration register 0x0032. opposite logic states prevail for the mask bcr bit in the message bc control word and the broadcast command received (bcr) bit in the received rt status word. the table on page 27 shows how the broadcast command received (bcr) bit in the received rt status word affects masked status set. HI-6130, hi-6131
holt integrated circuits 85 bit no. mnemonic r/w reset function 10 gdbt r 0 good data block transfer. indicating status for the last transmit-data message, this bit is set to logic 1 after completion of an error-free rt-to-bc transfer, rt-to-rt transfer, or transmit mode command with data. this bit is reset to logic 0 following any message in which error occurs. this bit is always logic 0 after completion of a bc-to-rt transfer, a receive mode command with data, or any mode command without data. this bit can be used to determine when the transmit portion of an rt-to-rt message was error-free: a block status word for an rt-to-rt message having both the error flag and good data block transfer bits set indicates that the transmitting rt responded correctly, but an error was detected in the receiving rt portion of the message. this bit is not affected by the device loop back function. 9 fmterr r 0 format error. this bit is logic 1 when the received data from the most recent message contains one or more violations of the mil-std-1553 message validation criteria, including sync, encoding, parity, bit count or word count errors. this bit is also set if the received status word from the responding rt contains incorrect rt address bits 15:10. 8 noresp r 0 no response error. this bit is set to logic 1 when an rt fails to respond to a command, or responds later then the bc no response timeout time. the no response timeout delay is programmed using bc timeout select bits 15-14 in the bc confguration register 0x0032. 7 ? 2 gp7 ? gp2 r 0 general purpose flags 7-2. interpretation of these fag bits is user defned. these bits are set cleared or toggled by the host, through use of the bc general purpose flag register, or by the bc, through use of the flg instruction op code. 1 eq / gp1 r 0 equal / general purpose flag 1. this fag bit is manipulated using the same methods as general purpose flags 7-2, or may be set or cleared by two bc instruction op codes, compare to frame time counter (cft) or compare to message time counter (cmt). 0 lt / gp0 r 0 less than / general purpose flag 0 this fag bit is manipulated using the same methods as general purpose flags 7-2, or may be set or cleared by two bc instruction op codes, compare to frame time counter (cft) or compared to message time counter (cmt). HI-6130, hi-6131
holt integrated circuits 86 11.7. bus controller (bc) general purpose flag register (write 0x0037) set gpf7 set gpf4 set gpf3 w set gpf6 set gpf5 set gpf2 set gpf0 set gpf1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 clr gpf7 clr gpf4 clr gpf3 clr gpf6 clr gpf5 clr gpf2 clr gpf0 clr gpf1 0 mr reset host access bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sharing the same register address as the read-only bc condition code register, this 16-bit register is write-only. this register is written by the host to set, clear or toggle any combination of the 8 general-purpose fags 7-0 in the bc condition code register. when this register is written, general-purpose fags are modifed. reading register address 0x0037 returns the value in the bc condition code register, containing the modifed gp fag bits (see section 11.6 ). each general-purpose fag in the bc condition code register is mirrored twice in the general purpose flag register, once in the upper byte and once in the lower byte. bits asserted in the lower byte set the corresponding gp fag bits in the bc condition code register to 1. bits asserted in the upper byte clear the corresponding gp fag bits in the bc condition code register to 0. bits asserted in both the lower and upper bytes for a specifc gp fag toggles (inverts) the corresponding gp fag bit in the bc condition code register. when both bits are written to logic 0 state for a spe - cifc gp fag bit, no change occurs for that gp fag bit. the flg instruction op code operates similarly, as shown in the diagram in figure 5 . bit no. mnemonic r/w reset function 15 ? 8 clear gp7 ? gp2 w 0 clear general purpose flag 7-0. bits asserted in the upper byte clear the corresponding gp fag bits in the bc condition code register to 0. 7 ? 0 set gp7 ? gp2 w 0 set general purpose flag 7-0. bits asserted in the lower byte set the corresponding gp fag bits in the bc condition code register to 1. bits asserted in both the lower and upper bytes for gpx toggles that gp fag bit in the bc condition code register. 11.8. bus controller (bc) general purpose queue pointer register (0x0038) msb 1 1 0 0 0 0 0 0 0 0 0 0 0 0 lsb r 0 0 general purpose queue ram address rw r mr reset host access bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 this 16-bit register is a combination of read-only and read-write bits. this register contains 0x00c0 after mr pin master reset. the initialized value represents the base address for the 64-word bc general purpose queue. the host can overwrite the default 0x00c0 value, but low order bits 5-0 and bit 15 must equal logic 0 for the initialized value. these bits cannot be set to logic 1 by a host write cycle. the general purpose queue provides a way for the bus controller message sequencer to convey various information to the external host. the bc instruction set includes op codes that push data values onto this queue, including immedi - ate data values, the block status word from the most recent message, the time tag register count, or the contents of a specifed memory address. HI-6130, hi-6131
holt integrated circuits 87 the general purpose queue is implemented as a 64-word circular buffer. this register always points to the next queue address to be written, the address following the last queue location written by the bus controller. this queue pointer rolls over from bits 5:0 = 11111 to 00000, every 64th word written. (bits 15:6 are static.) if enabled in the bc interrupt enable register, the bcgpq interrupt will be generated each time queue pointer rollover occurs. 11.9. bus controller (bc) time tag counter (0x0043) r mr reset host access bit 15 14 13 12 11 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 8 7 6 5 4 3 2 1 0 register value msb lsb 11.10. bus controller (bc) time tag counter high (0x0044) r mr reset host access bit 15 14 13 12 11 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 8 7 6 5 4 3 2 1 0 register value msb lsb these registers are read-only and are cleared after mr pin master reset. the bus controller can be confgured for either 16- or 32-bit time base counting in the time tag counter confguration register. when confgured for 16-bit time base operation, register 0x0043 contains the entire 16-bit count. when confgured for 32-bit time base operation, count bits 31-16 reside in register 0x0044 while register 0x0043 contains bits 15-0. for programmed bus controller action, instruction op codes are provided for loading a time tag count value, or pushing the current time tag count onto the bc general purpose queue. if confgured for 32-bit time base operation, separate op codes are provided for loading the upper or lower words individually, or pushing the individual words or simultane - ously pushing both words onto the bc general purpose queue: &rqjxudwlrq op code description 16-bit time base ltt lth ptt pth ptb load time tag count (parameter) into register 0x0043. not used for 16-bit time base. push time tag count from register 0x0043 onto bc gp queue. not used for 16-bit time base. not used for 16-bit time base. 32-bit time base ltt lth ptt pth ptb load low time tag count (parameter) into register 0x0043. load high time tag count (parameter) into register 0x0044. push low time tag count from register 0x0043 onto bc gp queue. push high time tag count from register 0x0044 onto bc gp queue. push low and high time tag counts from register 0x0043 and 0x0044 onto bc gp queue (simultaneous 32-bit count capture) the host can bypass bc instruction list execution to exercise direct control over the bc time tag counter. by writing bits 13-12 in the time tag counter confguration register 0x0039, the host can clear time tag count to zero, or load the current value contained in the bc time tag utility register(s) into the bc time tag counter(s). finally, the bc time tag match register(s) provide capability for host interrupts when the time tag count reaches any predetermined 16- or 32-bit value. HI-6130, hi-6131
holt integrated circuits 88 11.11. bus controller (bc) time tag utility register (0x0045) rw mr reset host access bit 15 14 13 12 11 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 8 7 6 5 4 3 2 1 0 register value msb lsb 11.12. bus controller (bc) time tag utility high register (0x0046) rw mr reset host access bit 15 14 13 12 11 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 8 7 6 5 4 3 2 1 0 register value msb lsb these registers are read-write and are cleared after mr pin master reset. this utility register pair is used for simul - taneously loading a 16- or 32-bit value into the bc time tag counter. when loading, the value contained in utility reg - ister 0x003d is copied into bc time tag counter register 0x0043. if the bc is confgured for 16-bit time base, register 0x0043 contains the entire 16-bit count. if confgured for 32-bit time base operation, count bits 31-16 are simultane - ously copied from utility register 0x003e into bc time tag counter register 0x0044. please refer to the description for bits 13-12 in the time tag counter confguration register (0x0039) on page 45 . 11.13. bus controller (bc) time tag match register (0x0047) rw mr reset host access bit 15 14 13 12 11 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 8 7 6 5 4 3 2 1 0 register value msb lsb 11.14. bus controller (bc) time tag match high register (0x0048) rw mr reset host access bit 15 14 13 12 11 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 8 7 6 5 4 3 2 1 0 register value msb lsb these registers are read-write and are cleared after mr pin master reset. when the bcttm bit 5 is logic 1 in the hardware interrupt enable register 0x000f, an interrupt occurs when the bc time tag count matches the value stored in this register pair. if the bc is confgured for 16-bit time base, match register 0x0045 is compared to time base count register 0x0043 for match determination. if confgured for 32-bit time base operation, count bits 31-16 in match register 0x0046 is also compared to bc time tag counter register 0x0044 for match determination. please refer to the descrip - tion for bcttm bit 5 in the hardware interrupt registers in section 9.7 . HI-6130, hi-6131
holt integrated circuits 89 11.15. bus controller interrupt registers and their use section 9.4 on page 36 through section 9.6 describe how the host uses three hardware interrupt registers, the interrupt log buffer and the interrupt count & log address register to manage interrupts. when the bus controller is enabled, three additional registers are dedicated to bus controller interrupts. comparable to the hardware interrupt register triplet, the bus controller has ? a bc interrupt enable register to enable and disable interrupts ? a bc pending interrupt register to capture the occurrence of enabled interrupts ? a bc interrupt output enable register to enable irq output to host, for pending enabled interrupts each individual bit in all three registers is mapped to the same interrupt-causing event when the corresponding interrupt condition is enabled. numerous interrupt options are available for the bc. at initialization, bits are set in the bc interrupt enable register to identify the interrupt-causing events for the bc which are heeded by the hi-613x. most bus controller applications only use a subset of available bc interrupt options. interrupt-causing events are ignored when their corresponding bits are reset in the bc interrupt enable register. setting an interrupt enable register bit from 0 to 1 does not trigger interrupt recognition for events that occurred while the bit was zero. whenever a bus controller interrupt event occurs (and the corresponding bit is already set in the bc interrupt enable register), these actions occur: ? the interrupt log buffer is updated. ? a bit corresponding to the interrupt type is set in the bc pending interrupt register. the type bit is logically-ored with the preexisting register value, retaining bits for prior, unserviced bc interrupts. ? bc interrupt pending (bcip) bit 0 is set in the hardware pending interrupt register. the bcip bit is logically- ored with the preexisting register value, retaining bits for unserviced hardware interrupts and the preexisting status of the mtip and rtip (bus monitor and rt) interrupt pending bits. ? if the matching bit is already set in the bc interrupt output enable register, an irq output occurs. if the matching bit in the bc interrupt output enable register was not already set (i.e., low priority polled interrupt), the host can poll the bc pending interrupt register to detect the occurrence of bc interrupts, indicated by non-zero value. reading the bc pending interrupt register automatically clears it to 0x0000. a single irq host interrupt output signal is shared by all enabled interrupt conditions having bits set in the four interrupt output enable registers (hardware, bc, rt and smt or imt). multiple interrupt-causing events can occur simultaneously, so single or simultaneous interrupt events can assert the irq host interrupt output. when the host receives an irq signal from the device, it identifes the event(s) that triggered the interrupt. section 9.4 describes two methods for identifying the interrupt source(s). one scheme uses the three low order bits in the hardware pending interrupt register to indicate when bc, rt, smt and/or imt interrupts occur. when bcip (bc interrupt pending) bit 0 is set in the hardware pending interrupt register, the bc pending interrupt register contains a nonzero value and may be read next to identify the specifc bc interrupt event(s). or, the host can directly interrogate the interrupt count & log address register, followed by the interrupt log buffer. data sheet section 9.4 has a detailed description. HI-6130, hi-6131
holt integrated circuits 90 11.15.1. bus controller (bc) interrupt enable register (0x0010) bcgpq bctrap bcwdt st atset bcirq2 bcirq0 bcirq1 bceom reserved bcretry 0 cstkerr 0 0 0 0 0 0 0 0 0 0 0 0 reserved bcmerr rw selmsg 0 reserved bcirq3 0 0 r mr reset host access bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 11.15.2. bus controller (bc) pending interrupt register (0x0007) bcgpq bctrap bcwdt st atset bcirq2 bcirq0 bcirq1 bceom reserved bcretry 0 cstkerr 0 0 0 0 0 0 0 0 0 0 0 0 reserved bcmerr selmsg 0 reserved bcirq3 0 0 r mr reset host access bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 11.15.3. bus controller (bc) interrupt output enable register (0x0014) bcgpq bctrap bcwdt st atset bcirq2 bcirq0 bcirq1 bceom reserved bcretry 0 cstkerr 0 0 0 0 0 0 0 0 0 0 0 0 reserved bcmerr rw selmsg 0 reserved bcirq3 0 0 r mr reset host access bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 three registers govern bc interrupt behavior: the bc interrupt enable register, the bc pending interrupt register and the bc interrupt output enable register. when a bit is set in the bc interrupt enable register, the correspond - ing bc interrupt is enabled. when a bit is reset in this register, the corresponding interrupt event is unconditionally disregarded. setting a register bit from 0 to 1 does not trigger interrupt recognition for events that occurred while the bit was zero. when an enabled bc interrupt event occurs, the corresponding bit is set in the bc pending interrupt register and the interrupt log buffer is updated. to simplify interrupt decoding, bcip bit 0 in the hardware pending interrupt register is also set whenever a message sets at least one bit in the bc pending interrupt register. if the corresponding bit is set in the bc interrupt output enable register, the irq output is asserted at message completion. the bc interrupt output enable register establishes two priority levels: high priority interrupts generate an irq output while low priority interrupts do not. both priority levels update the pending interrupt register and inter - rupt log buffer. the host can detect low priority (masked) interrupts by polling pending interrupt registers. the table below frst describes the common bits 15-3 in all three bc interrupt registers and then describes register- to-register differences for bits 2-0. HI-6130, hi-6131
holt integrated circuits 91 bit no. mnemonic function 15 bcwdt bc watchdog timer interrupt. the bc frame timer expired. 14 selmsg bc selected message interrupt. the completion of a mil-std-1553 message that has bit 4 set (eom) in the message block control word. 13 bcgpq bc general purpose queue rollover interrupt. the 64-word circular bc general purpose queue pointer rolled over to its base address value. 12 bcretry bc retry interrupt. the occurrence of a retried message by the bc. if enabled, the interrupt will occur after the last enabled message retry (one or two) regardless of the outcome, successful or unsuccessful. 11 cstkerr bc call stack pointer error interrupt. the bc subroutine stack depth was violated due to an overfow or underfow condition. call stack level is incremented each time a bc subroutine call op code (cal) is executed. call stack level is decremented each time a bc subroutine return op code (rtn) is executed. the allowed range for the call stack level is 0-7. an interrupt occurs when a cal op code executes when stack level is 7, an interrupt also occurs when a rtn op code executes when stack level is 0. 10 bctrap bc trap interrupt. two conditions can assert this interrupt: the bc fetched an illegal op code. the bc operation stops when the current 1553 message is complete. an illegal op code is either undefned, fails parity check, and/or has the wrong value for bits 9-5. when this occurs, bcrun bit 15 resets to logic 0 in the bc condition code and gp flag register 0x0037. when the chkfmt bit 13 is set in the bc confguration register, the bc control word message format bits 2-0 (mode command, rt-rt and broadcast message fags) are compared to the stored value(s) for the message command word(s) following the control word in the message block. when mismatch occurs between control word format bits and command word(s), the bctrap interrupt is asserted, if enabled. bc instruction list execution continues, so this condition can be differentiated from illegal op code because bcrun bit 15 remains high in the bc condition code and gp flag register, 0x0037. for mode command or broadcast mismatch, the stored message block command word(s) are transmitted. for rt-rt format mismatch, rt-rt bit 1 in the control word has priority, determining whether the message block is treated as an 8- or 16-word entity. for rt-rt format mismatch, message failure is likely for this message or the next message block , since the message block boundary is misplaced. the chkfmt option bit detects bc programming problems in the development phase. the option is normally disabled in the feld. HI-6130, hi-6131
holt integrated circuits 92 bit no. mnemonic function 9 statset bc status set interrupt. the bc received an rt status word containing the wrong rt address feld, or having an unexpected bit value for at least one of the eight non-reserved status bits. the expected value for these bits (excluding the bcr bit) is usually 0. the bcr (broadcast command received) bit can have an expected value of 1 when bcr mask enable bit in the bc confguration register is logic 0. in this case, the mask broadcast bit in the message block control word shows the expected value of the status word bcr bit. if the control words mask broadcast bit is logic 1, the expected value of bcr in the rt status word is logic 1. 8 ? 5 bcirq3:0 bc interrupt request bits 3-0. when this 4-bit feld is nonzero, the bc executed an irq op code. the value of bits 8:5 will equal the value of the 4 lsbs in the parameter associated with the irq op code. the user may defne the 4- bit pattern to suit application requirements. 4 bcmerr bc message error interrupt. a non-broadcast message ended with rt status word containing the me message error status bit set. 3 bceom bc end of message interrupt. the successful completion of a message, regardless of validity. 2 ? 0 reserved bits 2-0 cannot be written, and read back 000. HI-6130, hi-6131
holt integrated circuits 93 12. simple monitor terminal (smt) the hi-613x can operate as an autonomous mil-std-1553 bus monitor, requiring minimal host support. two fundamentally different monitor modes are offered. each of these modes has a separate data sheet section describing registers used and operational details. information regarding the alternative irig-106 monitor terminal (imt) begins in section 14 . 12.1. overview simple monitor terminal (smt) mode has its own dedicated time tag counter, and can use either a 16- or 48-bit time tag scheme. the smt monitor utilizes two circular buffers in ram: a command buffer and a data buffer. each recorded mil-std-1553 message appends a fxed length entry into the command buffer and a variable length entry into the data buffer. the smt message records a fxed length message block in the command buffer for each mil-std-1553 message. the advantage of fxed length command buffer message blocks is that the host can quickly jump to the block start address for any message. the number of words added to the data buffer for each message depends on the mil-std-1553 message type, ranging from zero (broadcast mode command without data) to 35 words (for a 32 data word rt-rt command). in smt mode, both circular buffers are fully utilized for recording message data. unlike imt mode, there is no option for generating a data header or data trailer. smt monitor mode allows selective monitoring of mil-std-1553 messages, based on the address, subaddress and t/ r status in each monitored command word, or can monitor all messages, when preferred. the smt monitor offers fexible interrupt options. in master confguration register 0x0000, mtena bit 8 is logically anded with the mtrun input pin to enable the smt monitor. if the mtrun input pin or master confguration register bit 8 equals logic 0, bus monitor operation is disabled. when the pin and master confguration register mtena bit 8 are both logic 1, the bus monitor is enabled. operation commences when the receiver frst decodes mil-std-1553 activity meeting the start record criteria selected by bits 6-5 in the mt confguration register 0x0029. if monitor operation is underway when master confguration register mtena bit 8 or mtrun input pin becomes logic 0, monitor operation stops after completion of any message already underway. the hi-613x is confgured for smt operation by writing bits 1-0 in the mt confguration register 0x0029. when mt confguration register bits 1-0 equal 11, the smt operates with 16-bit time tag resolution and each recorded mil-std-1553 message adds a four word entry in the circular command buffer. this is summarized in table 9 . table 9. message block in circular command buffer for smt monitor using 16-bit time tag message word block word name word function when using 16-bit time tag word 3 message command word message command word. the mil-std-1553 command word that initiated the message. for an rt-rt message, receive command word 1 is stored here; transmit command word 2 is the frst stored word in the message data block. word 2 data block pointer starting address in the data buffer for the corresponding message data block. HI-6130, hi-6131
holt integrated circuits 94 message word block word name word function when using 16-bit time tag word 1 message time stamp bits 15 ~ 0 sixteen bit message time stamp. word 0 is the frst word in the command buffer entry for each message. word 0 block status word message block status word, defned in section 12.2 . word 0 is the frst word in the command buffer entry for each message. when mt confguration register bits 1-0 equal 01, the simple message monitor operates with 48-bit time tag resolution. each mil-std-1553 message adds an 8-word entry in the circular command buffer. this is summarized in table 10 . the expanded message block accommodates two additional time tag words, a message length word and a response time word not found when using 16-bit time tag resolution. table 10. message block in circular command buffer for smt monitor using 48-bit time tag message word block word name word function when using 16-bit time tag word 7 message command word message command word. the mil-std-1553 command word that initiated the message. for an rt-rt message, receive command word 1 is stored here; transmit command word 2 is the frst stored word in the message data block. word 6 data block pointer starting address in the data buffer for the corresponding message data block. word 5 message length word (bytes) the message length word indicates the number of bytes stored in the message data block. the range is 0 to 70 bytes, corresponding to 0 to 35 16-bit words stored. word 4 response time word the response time word contains two 8-bit felds: ? bits 15 ~ 8 contains gap2 ? bits 7 ~ 0 contains gap1 all gap values are measured from mid-parity zero crossing of the preceding word, to the mid-sync zero crossing of the status word (the gap dead time interval plus 2 s). time resolution is 100 ns per lsb, so the maximum indicated gap time for gap1 or gap2 is 25.5 s. for rt-rt messages, the gap1 byte indicates transmit rt response time, and the gap2 byte indicates received rt response time. for all other messages, the gap1 byte indicates the only rt response time, and the gap2 byte reads 0x00. word 3 block status word message block status word, defned in section 12.2 . HI-6130, hi-6131
holt integrated circuits 95 message word block word name word function when using 16-bit time tag word 2 message time stamp bits 47 ~ 32 upper 16-bit word of message 48-bit time stamp. word 1 message time stamp bits 31 ~ 16 middle 16-bit word of message 48-bit time stamp. word 0 message time stamp bits 15 ~ 0 lower 16-bit word of message 48-bit time stamp. word 0 is the frst word in the command buffer entry for each message. the circular command buffer address range is bounded by the values in address list words 0 and 2. the circular data buffer address range is bounded by the values in address list words 4 and 6. the next address words 1 and 5 must be initialized by the host for the frst data written after reset, usually to match the word 0 and word 4 values respectively. thereafter, these values are maintained by the device each time a new mil-std-1553 message is recorded. two optional buffer address interrupts are offered. when enabled, a command or data buffer address interrupt occurs whenever the matching ram address in the buffer is written. the address list contains the address values for these optional buffer utilization interrupts. for smt mode, the 8-word monitor address list is defned in table 11 . table 11. monitor address list for smt mode address list word word name description word 7 data buffer interrupt address host initialized with a ram address value if this interrupt is enabled. if enabled, an interrupt occurs when the matching ram address is written. address must occur within the range bounded by words 4 and 6. word 6 data buffer end address host initialized, defnes smt data buffer upper (rollover) address. word 5 data buffer next address must be host initialized , usually to match smt data buffer start address. updated by device each time a new mil-std-1553 message is recorded. this value advances through the address range in circular buffer fashion. word 4 data buffer start address host initialized, defnes smt data buffer lower address boundary. word 3 command buffer interrupt address host initialized with a ram address value if this interrupt is enabled. if enabled, an interrupt occurs when the matching ram address is written. address must occur within the range bounded by words 0 and 2. HI-6130, hi-6131
holt integrated circuits 96 address list word word name description word 2 command buffer end address host initialized, defnes smt circular command buffer upper (rollover) address. word 1 command buffer next address must be host initialized , usually to match command buffer start address. updated by device each time a new mil-std-1553 message is recorded. this value advances through the address range in circular buffer fashion. word 0 command buffer start address host initialized, defnes smt circular command buffer lower address boundary. word 0 occurs at the address list base address in register 0x002f. for each monitored mil-std-1553 command, the written command buffer entry is fxed at 4 or 8 words, depending on selected time tag resolution. depending on mil-std-1553 message type, the written data buffer entry varies in length, ranging from zero words (for broadcast mode code commands without data) to 35 words (for an rt-to-rt message with 32 data words). simple monitor terminal data storage is summarized in figure 7 . HI-6130, hi-6131
holt integrated circuits 97 increasing memory address message ti me stamp, bits 47-32 block status wo rd for message message length wo rd response ti me wo rd datab lock pointer for message command wo rd for message message ti me stamp, bits 31-16 message ti me stamp, bits 15-0 command buffer command buffer command buffer single message block command buffer single message block block status wo rd for message datab lock pointer for message command wo rd for message message ti me stamp, bits 15-0 command buffer data buffer blocks for each message data buffer blocks for each message dat aw ords for message n-1 dataw ords for message n+1 dataw ords for message n data buffer dat a buffer dat aw ords for message n-1 dataw ords for message n+1 dataw ords for message n dat a buffer dat a buffer initialized for 16-bit time stamp register 0x0029 bits 1-0 equal 01 initialized for 48-bit time stamp register 0x0029 bits 1-0 equal 11 1-32 data w ords: data n data 1 ......... t ransmitting rt status w ord 1-32 data w ords: data n data 1 ......... receiving rt status w ord rt-to-bc (transmit) command bc-to-rt (receive) command 1-32 data w ords: data n data 1 ......... receiving rt status w ord 1-32 data w ords: data n data 1 ......... 1-32 data w ords: data n data 1 ......... broadcast bc-to-rt (receive) command no broadcast v ersion non-broadcast message types corresponding broadcast messages command w ord 2 to t ransmit rt rt-to-rt command broadcast rt-to-rt command rt status w ord t ransmitting rt status w ord transmit mode code with data receive mode code with data transmit or receive mode code without data mode data w ord receiving rt status w ord mode data w ord mode data w ord command w ord 2 to t ransmit rt no broadcast v ersion for broadcast mode codes without data (mc0 - mc15) no status or data w ords are recorded the number of words stored in the data buffer varies from message to message, based on message type. t ransmitting rt status w ord t ransmitting rt status w ord command buffer broadcase receive mode code with data figure 7. simple monitor terminal (smt) data storage HI-6130, hi-6131
holt integrated circuits 98 12.2. smt block status word (bsw) description the smt bus monitor stores a block status word in the circular command buffer for each monitored mil-std-1553 message. this word provides information regarding message status, the bus on which the message occurred, whether errors occurred during the message, and the type of occurring errors. the block status word for smt mode is defned as follows: smt block status word with extended status bits enabled (not irig-106 chapter 10 compliant) rrgsa 0 bit host access 0 0 0 0 0 0 0 0 0 cwce 0 rrcw2 mr reset 0 le dsr se we 0 reserved rw eo tm som gdb rr ige bid 0 eom 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 bit no. mnemonic r/w reset function 15 eom r/w 0 end of message. bit 15 is set upon completion of a monitored message, whether or not errors occurred. when eom is set, som bit 14 is concurrently reset. 14 som r/w 0 start of message. bit 14 is set to logic 1 approximately 3-4 s after completion of a valid command word, and is reset to logic 0 at the end of the message. if the monitor uses message fltering, som is only set for monitored messages. 13 bid r/w 0 bus id (bus b / bus a ). bit 13 indicates the bus id for the message. this bit is logic 0 for a message occurring on bus a. this bit is logic 1 for a message occurring on bus b. HI-6130, hi-6131
holt integrated circuits 99 bit no. mnemonic r/w reset function 12 eo r/w 0 error occurred flag. this bit indicates a message error was encountered. this bit is set when one or more of the following conditions are true (logical-or): ? an unfnished message is superseded by another valid command ? bit 10 illegal gap error is set ? bit 9 response timeout is set ? bit 5 length (word count) error is set ? bit 4 sync type error is set ? bit 3 invalid word error is set ? bit 2 rt-rt gap / sync / address error is set ? bit 1 rt-rt command word 2 error is set (except as noted) ? bit 0 command word content error is set (except as noted) there are three exceptions where register bit 0 or 1 is set without affecting bit 12 state: bit 1 rt-rt command word 2 errors that do not assert bit 12 ? rt-rt transmit command word 2 subaddress feld equals 00000 or 11111 (mode code command indicated) ? rt-rt transmit command word 2 has the same rt address as receive command word 1 bit 0 command word content error that does not assert bit 12 ? undefned receive mode code 0~15 decimal. 11 rr r/w 0 rt-to-rt transfer when logic 1, bit 11 indicates an rt-to-rt message, beginning with two contiguous command words. 10 ige r/w 0 illegal gap error when logic 1, bit 10 indicates an illegal gap occurred on the bus, other than response timeout. 9 tm r/w 0 response timeout when logic 1, bit 9 indicates a response timeout occurred. this bit is set if an rt status word associated with this message failed to arrive within the response time interval specifed by bits 15-14 in the mt confguration register 0x0029. 8 gdb r/w 0 good data block transfer bit 8 is set to logic 1 following completion of a valid, error-free message. this bit is reset to logic 0 following completion of a message in which error occurred. if an rt responds to a transmit command with busy status and does not transmit the commanded data words, this is not considered a message error that causes gdb reset. HI-6130, hi-6131
holt integrated circuits 100 bit no. mnemonic r/w reset function 7 dsr r/w 0 data buffer rollover bit 7 is logic 1 to indicate that this message overran the monitor data buffer end address, causing the storage pointer to roll over to the base address. 6 sfs r/w 0 status flag set bit 6 is logic 1 when a status bit was set in an rt status word response. 5 le r/w 0 word count (length) error bit 5 indicates that the number of data words transmitted by the bc or rt differs from the word count specifed in the command word. an rt status word with the busy bit set will not cause word count error. a transmit command with response timeout will not cause word count error. 4 se r/w 0 sync type error bit 4 is logic 1 to indicate that a bc transmitted data sync with a command word, or a command / status sync occurred with data word, or an rt responded with data sync in its status word and/or command/ status sync in a data word. 3 we r/w 0 invalid word error (we) bit 3 is logic 1 indicate on invalid word error occurred. this includes manchester decoding errors in the sync pattern or word bits, or the wrong number of bits in the word, or parity error. 2 rrgsa r/w 0 rt-to-rt gap/sync/address error (rrgsa) bit 2 is logic 1 if one or more of the following rt-rt message conditions occur: ? mt gap check is enabled (bit 12 equals 1 in register 0x0029) and an rt status word is received having a response time less than 4s, per mil-std-1553b (mid-parity to mid-sync). in other words, the bus dead time was less than 2s. ? one of the rts responds with an invalid status word, having a sync error, a manchester encoding error, bit count error and/or parity error ? one of the rt status words contains an rt address that differs from the rt address in the corresponding command word. 1 rrcw2 r/w 0 rt-to-rt command word 2 error (rrcw2) bit 1 is logic 1 if an rt-to-rt message occurs (two contiguous command words) with one or more of the following illogical conditions: ? transmit command word 2 t/ r bit equals 0 (receive) ? transmit command word 2 subaddress feld equals 00000 or 11111 (mode command indicated) ? transmit command word 2 has the same rt address as receive command word 1 ? transmit command word 2 has sync error HI-6130, hi-6131
holt integrated circuits 101 bit no. mnemonic r/w reset function 0 cwce r/w 0 command word content error (cwce) bit 0 is logic 1 if a received command word violates one or more mil- std-1553b requirements: ? a non-mode broadcast transmit command word occurred. (non- mode has 5-bit subaddress feld equal to decimal 1~30) ? a receive mode code command word was received with mode code in the range of 0~15 decimal (undefned) ? a broadcast transmit mode code command occurred having a mode code value for which broadcast is not allowed (mode code = decimal 0, 2, 16, 18 or 19) 12.3. smt message filter table the simple monitor terminal can select messages for monitoring through the use of a 128-word mt filter table, located at fxed ram address 0x0100. when the table bit corresponding to a new message command word is logic 1, that message is ignored by the monitor. if the table bit is logic 0, that message is recorded. after mr master reset, 100% of mil-std-1553 messages are monitored, since the entire table address range 0x0100 through 0x017f inclusive is 0x0000. the result is that every valid command word, received on an idle bus, marks the start of a new mil-std-1553 message recorded by the monitor. the message filter table is addressed using three felds in the received command word: the 5-bit rt address feld, the t/ r transmit/receive bit, and the msb of the 5-bit subaddress feld. this is illustrated in figure 8 . bit fields comprising each received command word command sync terminal address ta4:0 subaddress sa4:0 word count (mode code) wc4:0 t/ bit r filter table address p 0 0 1 0 0 0 0 0 0 figure 8. deriving the monitor filter table address from the received command word HI-6130, hi-6131
holt integrated circuits 102 each rt address from 0 to 31 decimal has four 16-bit table words: two words enable/disable individual receive subaddresses, two more words enable/disable individual transmit subaddresses. the frst four table words apply to subaddress 0 and are illustrated in table 12 . this 4-word pattern repeats for all 32 subaddresses, 0-31 decimal. table 12. smt message filter table filter table addresses 0x017c - 0x017f rt address 31 subaddresses (4 words) filter table addresses 0x0178 - 0x017b rt address 30 subaddresses (4 words) . . . . . . filter table addresses 0x0108 - 0x010b rt address 2 subaddresses (4 words) filter table addresses 0x0104 - 0x0107 rt address 1 subaddresses (4 words) filter table address 0x0103 rt address 0, transmit subaddresses 31 to 16 word bit # 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 transmit sa 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 filter table address 0x0102 rt address 0, transmit subaddresses 15 to 0 word bit # 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 transmit sa 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 filter table address 0x0101 rt address 0, receive subaddresses 31 to 16 word bit # 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 receive sa 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 filter table address 0x0100 rt address 0, receive subaddresses 15 to 0 word bit # 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 receive sa 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 a subaddress message is monitored when the corresponding word bit equals logic 0. the message is not monitored when the bit equals 1. HI-6130, hi-6131
holt integrated circuits 103 13. simple monitor terminal (smt) register description in addition to the registers described here, a hi-6131 smt bus monitor also utilizes one or more memory address pointer registers (described in section 9.10 ) for managing spi read/write operations. this comment does not apply for parallel bus interface HI-6130 designs. 13.1. smt confguration register (0x0029) reserved mtto0 reserved mtttb1 mtttb0 mtsrr1 reserved reserved mtxmf gchk 0 mtto1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 smt / imt mtsrr0 mtcriw rw reserved 0 48btt w rw mr reset host access bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit no. mnemonic r/w reset function 15 ? 14 mtto1:0 r/w 0 mt time out select. this 2-bit feld selects the monitor no response time-out delay from four available selections. excluding rt-rt commands, the delay is measured from command word mid-parity bit to status word mid-sync. bit 15:14 bus dead time time out (excludes rt- rt) rt-rt time out 00 01 10 11 16s 21s 80s 138s 18s 23s 82s 140s 61s 66s 122s 180s for rt-rt commands, time out delay is measured per figure 8 in the rt validation test plan, sae as4111. that is, from mid-parity of the receive command to mid-sync of the frst received data word. this adds 40s for the embedded transmit command word and transmit-rt status word within this interval. 13 reserved w 0 bit 13 is not used by the bus monitor operating in smt mode. initialize this bit to logic 0. 12 gchk r/w 0 gap check. when this bit equals 1, the monitor evaluates inter-message gaps and rt response times for a minimum preceding bus dead time of 2 s. this dead time corresponds to an inter-message gap of 4s, measured per mil-std-1553, from mid-parity zero crossing of the preceding word, to mid-sync zero crossing of the following word. a minimum gap time violation results in a format error in the block status word for the message. when this bit equals 0 (recommended), the monitor does not check for short inter-message gap times. 11 ? 10 reserved r/w 0 bits 11-10 are not used by the bus monitor operating in smt mode. initialize these bits to logic 0. HI-6130, hi-6131
holt integrated circuits 104 bit no. mnemonic r/w reset function 9 ? 8 mtttb1:0 r/w 0 monitor time tag message bit select. this 2-bit feld selects the bit within the mil-std-1553 message where time stamp occurs. time stamp occurs at mid-bit transition: bit 9:8 time tag event 00 01 10 11 last bit of last word in message first bit of first (command) word in message last bit of first (command) word in message time tag disabled, stores time tag = 0 for options 00 and 10, the last bit precedes the words parity bit. for option 01, the first bit occurs 0.5s after command sync. while first word generally denotes a command word, message recording can begin with a data word when register bit 5 equals 1. 7 reserved r/w 0 bit 7 is not used by the bus monitor operating in smt mode. initialize this bit to logic 0. HI-6130, hi-6131
holt integrated circuits 105 bit no. mnemonic r/w reset function 6 ? 5 mtsrr1:0 r/w 0 mt start-record requirement 1:0. when register bits 6-5 equal 00, the mt starts recording a new mil-std-1553 message when a properly encoded, complete mil-std-1553 word with command sync is decoded: the command sync is followed by 16 properly encoded data bits plus a 17th parity bit expressing odd parity. no data is recorded until this condition is met. this is the usual setting. (default setting) when register bits 6-5 equal 01, the mt starts recording a new mil-std-1553 message when a properly encoded, complete mil-std-1553 word with command sync or data sync is decoded. the properly encoded command sync (or data sync) is followed by 16 properly encoded data bits plus a 17th parity bit expressing odd parity. if recording begins with data sync, the sync error fag will be set in the block status word. when register bits 6-5 equal 10, the mt starts recording a new mil-std-1553 message upon detection of a properly encoded command sync with two contiguous data bits . if the properly encoded command sync with two contiguous data bits does not result in a valid command word, the invalid word error is set in the block status word. this selection begins recording for complete mil-std-1553 command words as well as for command word fragments, or command words with bad parity. under some circumstances, this record option might be helpful for debugging mil-std-1553 communication failure. when register bits 6-5 equal 11, the mt starts recording new bus activity upon detection of any properly encoded sync (command or data) with two contiguous data bits . this selection begins recording for complete mil-std-1553 command or data words as well as for word fragments, or words with bad parity. if the properly encoded sync with two contiguous data bits does not result in a valid manchester ii word, the invalid word error is set in the block status word. if recording begins with data sync, the sync error fag will be set in the block status word. under some circumstances, this record option might be helpful for debugging mil-std-1553 communication failure. 4 mtcriw r/w 0 mt continue recording after invalid word. when bit 4 equals 0, the mt stops recording an incomplete message when an invalid mil-std-1553 word is decoded. the invalid word is not stored, and the mt awaits word detection per register bits 6-5 before the next mil-std-1553 message is recorded. (default) when bit 4 equals 1, the mt continues recording an incomplete message when an invalid mil-std-1553 word is decoded. the invalid word is stored and the mt continues monitoring the message until completion or time-out occurs. 3 reserved r/w 0 bit 3 is not used by the bus monitor operating in smt mode. initialize this bit to logic 0. HI-6130, hi-6131
holt integrated circuits 106 bit no. mnemonic r/w reset function 2 mtxmf r/w 0 extended message flag enable. usually register bit 2 is set to logic 1 to enable expanded status/error fags, occupying the reserved bit positions in the irig-106 block status word. when register bit 2 equals 0, the recorded status/error fags are limited to the defned bits in the irig-106 block status word. this is described in section 14.6 . 1 48btt r/w 0 48-bit time tag / 16-bit time tag when register bit 1 equals 0, the smt time tag counter operates with 16- bit resolution and the recorded entry for each mil-std-1553 message in the command buffer is four 16-bit words. when register bit 1 equals 1, the smt time tag counter operates with 48-bit resolution. to record the 48-bit time count, the entry for each mil- std-1553 message in the command buffer is eight 16-bit words. two of the words added are used for response time and message length words. see section 13.5 . 0 smt / imt r/w 0 select simple monitor terminal (smt) or irig-106 monitor terminal (imt). for smt operation, this register bit must be logic 1. 13.2. smt bus monitor address list start address register (0x002f) rw mr reset host access bit 15 14 13 12 11 10 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 0 9 8 7 6 5 4 3 2 1 0 register value msb lsb this 16-bit register is read-write and is fully maintained by the host. after mr pin master reset, this register is initialized with 0x00b0, the default base address of the mt address table in device ram. the host can overwrite the default base address. this register is not affected by mt soft reset, when the mtreset bit is asserted in the master status and reset register, 0x0001. the address list for smt mode is summarized in table 11 on page 95 . 13.3. smt next message command buffer address (0x0030) r mr reset host access bit 15 14 13 12 11 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 8 7 6 5 4 3 2 1 0 register value msb lsb this 16-bit register is read-only and is updated by the mt upon completion of a monitored mil-std-1553 message. this register is cleared after mr pin master reset or by mt soft reset, when the mtreset bit is asserted in the master status and reset register, 0x0001. this register contains the address for the frst word to be stored in mt command buffer, for the next mil-std-1553 message. after the frst post-reset message is logged, this register mirrors the value contained in smt address list word 1 (see table 11 on page 95 ). HI-6130, hi-6131
holt integrated circuits 107 the mt logic only updates this next message address register after message completion. therefore, after reset or after the host has changed the mt address list start address register 0x002f, this register does not contain a pointer address until processing for the next message is completed. if the read value equals zero, the next message address is the command buffer starting address. 13.4. smt last message command buffer address (0x0031) r mr reset host access bit 15 14 13 12 11 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 8 7 6 5 4 3 2 1 0 register value msb lsb this 16-bit register is read-only and is updated by the mt upon completion of a monitored mil-std-1553 message. this register is cleared after mr pin master reset or by mt soft reset, when the mtreset bit is asserted in the master status and reset register, 0x0001. this register contains the ram address for the frst word stored in the circular command buffer for the last completed mil-std-1553 message. 13.5. smt bus monitor time tag count register (0x003a) r mr reset host access bit 15 14 13 12 11 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 8 7 6 5 4 3 2 1 0 register value msb lsb when mt confguration register bits 1-0 equal 11, the simple message monitor operates with 16-bit time tag resolution and register 0x003a contains the full 16-bit time tag count. when mt confguration register bits 1-0 equal 01, the simple message monitor operates with 48-bit time tag resolution and the full time tag count requires the above register plus two additional registers: 13.6. smt bus monitor time tag count mid register (0x003b) r mr reset host access bit 15 14 13 12 11 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 8 7 6 5 4 3 2 1 0 register value msb lsb 13.7. smt bus monitor time tag count high register (0x003c) r mr reset host access bit 15 14 13 12 11 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 8 7 6 5 4 3 2 1 0 register value msb lsb HI-6130, hi-6131
holt integrated circuits 108 when confgured for 48-bit time base operation, count bits 47-17 reside in register 0x003c, count bits 31-16 reside in register 0x003b while register 0x003a contains bits 15-0. the host cannot directly write these registers but uses other methods to control or read time tag count. by writing bits 15-14 in the time tag counter confguration register 0x0039, the host can clear time tag count to zero, copy the cur - rent time count to the smt time tag utility register(s), or load the current value contained in the smt time tag utility register(s) into the smt time tag counter(s). finally, the smt time tag match register(s) provide capability for host interrupts when the time tag count reaches any predetermined 16- or 48-bit value. for further information, refer to the description of the time tag counter confguration register 0x0039. 13.8. smt bus monitor time tag utility register (0x003d) rw mr reset host access bit 15 14 13 12 11 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 8 7 6 5 4 3 2 1 0 register value msb lsb when mt confguration register bits 1-0 equal 11, the simple message monitor operates with 16-bit time tag resolution and register 0x003d is the only time tag utility register needed. when mt confguration register bits 1-0 equal 01, the simple message monitor operates with 48-bit time tag resolution and utility operations require the above register plus two additional registers: 13.9. smt bus monitor time tag utility mid register (0x003e) rw mr reset host access bit 15 14 13 12 11 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 8 7 6 5 4 3 2 1 0 register value msb lsb 13.10. smt bus monitor time tag utility high register (0x003f) rw mr reset host access bit 15 14 13 12 11 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 8 7 6 5 4 3 2 1 0 register value msb lsb these registers are read-write and are cleared after mr pin master reset. this utility register triplet is used for simultaneously loading or reading a 16- or 48-bit value into or from the smt time tag counter. please refer to the description for bits 15-14 in the time tag counter confguration register 0x0039 in section 9.9 . loading a 16-bit or 48-bit value into the smt time tag count register(s) when loading or clearing time tag count, the 16-bit value in time tag utility register 0x003d is copied into smt time tag count register 0x003a. if confgured for 48-bit time stamp operation, count bits 47-17 and count bits 31-16 are simultaneously copied from time tag utility registers 0x003f and 0x003e into smt time tag count registers 0x003c and 0x003b respectively. HI-6130, hi-6131
holt integrated circuits 109 capturing a 16-bit or 48-bit value from the smt time tag count register(s) when capturing time tag count, the 16-bit value in smt time tag count register 0x003a is copied into time tag utility register 0x003d. if confgured for 48-bit time stamp operation, count bits 47-17 and count bits 31-16 in smt time tag count registers 0x003c and 0x003b are simultaneously copied into time tag utility registers 0x003f and 0x003e respectively. 13.11. smt bus monitor time tag match register (0x0040) rw mr reset host access bit 15 14 13 12 11 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 8 7 6 5 4 3 2 1 0 register value msb lsb when mt confguration register bits 1-0 equal 11, the simple message monitor operates with 16-bit time tag resolu - tion and register 0x0040 is the only time tag utility register needed. when mt confguration register bits 1-0 equal 01, the simple message monitor operates with 48-bit time tag resolu - tion and time tag matching operations require the above register plus two additional registers: 13.12. smt bus monitor time tag match mid register (0x0041) rw mr reset host access bit 15 14 13 12 11 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 8 7 6 5 4 3 2 1 0 register value msb lsb 13.13. smt bus monitor time tag match high register (0x0042) rw mr reset host access bit 15 14 13 12 11 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 8 7 6 5 4 3 2 1 0 register value msb lsb these registers are read-write and are cleared after mr pin master reset. when the mtttm bit 6 is logic 1 in the hardware interrupt enable register 0x000f, an interrupt occurs when the mt time tag count matches the value stored in this register triplet. if the mt is confgured for 16-bit time tag, time tag match register 0x0040 is compared to time tag count register 0x003a for match determination. if confgured for 48-bit time tag operation, count bits 47-17 and 31-16 in time tag match registers 0x0042 and 0x0041 are also compared to mt time tag count registers 0x003c and 0x003b for 48-bit match determination. please refer to the description for mtttm bit 6 in the hardware interrupt registers described in section 9.7 . HI-6130, hi-6131
holt integrated circuits 110 13.14. smt bus monitor interrupt registers and their use section 9.4 on page 36 through section 9.6 describe how the host uses three hardware interrupt registers, the interrupt log buffer and the interrupt count & log address register to manage interrupts. when the smt is enabled, three additional registers are dedicated to smt interrupts. comparable to the hardware interrupt register triplet, the smt has ? an smt interrupt enable register to enable and disable interrupts ? an smt pending interrupt register to capture the occurrence of enabled interrupts ? an smt interrupt output enable register to enable irq output to host, for pending enabled interrupts each individual bit in all three registers is mapped to the same interrupt-causing event when the corresponding interrupt condition is enabled. numerous interrupt options are available for the smt. at initialization, bits are set in the smt interrupt enable register to identify the interrupt-causing events for the smt which are heeded by the hi-613x. most smt applications only use a subset of available smt interrupt options. interrupt-causing events are ignored when their corresponding bits are reset in the smt interrupt enable register. setting an interrupt enable register bit from 0 to 1 does not trigger interrupt recognition for events that occurred while the bit was zero. whenever an smt interrupt event occurs (and the corresponding bit is already set in the smt interrupt enable register), these actions occur: ? the interrupt log buffer is updated. ? a bit corresponding to the interrupt type is set in the smt pending interrupt register. the type bit is logically- ored with the preexisting register value, retaining bits for prior, unserviced smt interrupts. ? mt interrupt pending (mtip) bit 1 used by smt or imt is set in the hardware pending interrupt register. the mtip bit is logically-ored with the preexisting register value, retaining bits for unserviced hardware interrupts and the preexisting status of the bcip and rtip (bus controller and rt) interrupt pending bits. ? if the matching bit is already set in the smt interrupt output enable register, an irq output occurs. if the matching bit in the smt interrupt output enable register was not already set (i.e., low priority polled interrupt), the host can poll the smt pending interrupt register to detect the occurrence of smt interrupts, indicated by non-zero value. reading the smt pending interrupt register automatically clears it to 0x0000. a single irq host interrupt output signal is shared by all enabled interrupt conditions having bits set in the four interrupt output enable registers (hardware, bc, rt and smt or imt). multiple interrupt-causing events can occur simultaneously, so single or simultaneous interrupt events can assert the irq host interrupt output. when the host receives an irq signal from the device, it identifes the event(s) that triggered the interrupt. section 9.4 describes two methods for identifying the interrupt source(s). one scheme uses the three low order bits in the hardware pending interrupt register to indicate when bc, rt, smt and/or imt interrupts occur. when mt interrupt pending (mtip) bit 1 used by smt or imt is set in the hardware pending interrupt register, the smt pending interrupt register contains a nonzero value and may be read next to identify the specifc smt interrupt event(s). or, the host can directly interrogate the interrupt count & log address register, followed by the interrupt log buffer. data sheet section 9.4 has a detailed description. HI-6130, hi-6131
holt integrated circuits 111 13.14.1. smt bus monitor interrupt enable register (0x0011) reserved reserved reserved reserved dbufro dbufmat cbufmat mteom reserved 0 reserved 15 0 0 0 0 0 0 0 0 mtmerr rw reserved 0 cbufro 0 r reserved 0 reserved reserved mr reset host access bit 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 13.14.2. smt bus monitor pending interrupt register (0x0008) reserved reserved reserved reserved mteom reserved 0 reserved 15 0 0 0 0 0 0 0 0 mtmerr reserved 0 0 reserved 0 reserved reserved mr reset host access bit 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 r dbufro dbufmat cbufmat cbufro 13.14.3. smt bus monitor interrupt output enable register (0x0015) reserved reserved reserved reserved mteom reserved 0 reserved 15 0 0 0 0 0 0 0 0 mtmerr rw reserved 0 0 r reserved 0 reserved reserved mr reset host access bit 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 dbufro dbufmat cbufmat cbufro three registers govern smt interrupt behavior: the smt interrupt enable register, the smt pending interrupt register and the smt interrupt output enable register. when a bit is set in the smt interrupt enable register, the corresponding smt interrupt is enabled. when a bit is reset in this register, the corresponding interrupt event is unconditionally disregarded. setting a register bit from 0 to 1 does not trigger interrupt recognition for events that occurred while the bit was zero. when an enabled smt interrupt event occurs, the corresponding bit is set in the smt pending interrupt register and the interrupt log buffer is updated. to simplify interrupt decoding, mtip bit 1 in the hardware pending interrupt register is also set whenever one or more bits are set in the smt pending interrupt register. if the corresponding bit is already set in the smt interrupt output enable register, the irq output pin is asserted at pending interrupt register assertion. the smt interrupt output enable register establishes two priority levels: high priority interrupts generate an irq output while low priority interrupts do not. both priority levels update the smt pending interrupt register and the interrupt log buffer. the host detects low priority (masked) interrupts by polling smt pending interrupt register. the table below describes the bit descriptions shared by all three smt interrupt registers. HI-6130, hi-6131
holt integrated circuits 112 bit no. mnemonic function 15 ? 9 reserved these bits are not used in smt monitor mode. they should be initialized logic 0 in the smt interrupt enable register. these bits will always read logic 0 in the smt pending interrupt register. 8 cbufro command buffer rollover interrupt. the command buffer pointer value (word 1 in the smt address list) has rolled over to the command buffer start address (word 0 in the smt address list). 7 dbufro data buffer rollover interrupt. the data buffer pointer value (word 5 in the smt address list) has rolled over to the data buffer start address (word 4 in the smt address list). 6 cbufmat command buffer address match interrupt. the command buffer pointer value (word 1 in the smt address list) has reached the command buffer address match value in word 3 of the smt address list. 5 dbufmat data buffer address match interrupt. the data buffer pointer value (word 5 in the smt address list) has reached the data buffer address match value in word 7 of the smt address list. 4 smtmerr smt message error interrupt. a non-broadcast mil-std-1553 message ended with an rt status word containing the me message error status bit set. 3 smteom smt end of message interrupt. successful completion of a mil-std-1553 message, regardless of validity. 2 ? 0 reserved bits 2-0 cannot be written, and read back 000. HI-6130, hi-6131
holt integrated circuits 113 14. irig-106 monitor terminal (imt) the hi-613x can operate as an autonomous mil-std-1553 bus monitor, requiring minimal host support. two fundamentally different monitor modes are offered. each of these modes has a separate data sheet section describing registers used and operational details. information regarding the alternative simple monitor terminal (smt) may be found in section 12 . 14.1. overview irig-106 monitor terminal (imt) mode complies with irig-106, a comprehensive standard ensuring interoperability of aeronautical telemetry at united states military rcc member ranges. the telemetry group of the range commanders council maintains the irig-106 standard. chapter 10 of the standard defnes operation and interfaces for digital fight data recorders over a range of telemetry protocols, including mil-std-1553. further information on the irig-106 standard can be found at http://irig106.org/ the hi-613x is confgured for imt operation when bit 0 in the mt confguration register 0x0029 is logic 0. the imt always operates with 48-bit time tag resolution. in register 0x0000, mtena bit 8 is logically anded with the mtrun input pin to enable the bus monitor. if the mtrun input pin or mtena register bit equals logic 0, bus monitor operation is disabled. when the mtrun pin and mtena register bit are both logic 1, the bus monitor is enabled. operation commences when the receiver frst decodes mil-std-1553 activity meeting the start record criteria selected by bits 6-5 in the mt confguration register. if monitor operation is underway when the mtena register bit or mtrun input pin becomes logic 0, monitor operation stops and the open data packet is fnalized after completion of any message already underway. the holt irig-106 monitor terminal (hereafter called imt) uses a single storage buffer in device ram. recorded message data, message results and characteristics are stored in multiple-message data packets. as they occur, mil-std-1553 messages are appended to the end of the open data packet and time stamped with a 48-bit time tag value. by default, the imt records all mil-std-1553 messages, although it optionally records just selected messages, based on rt address, subaddress and transmit/receive status for each detected command word. the imt optionally generates a packet header and packet trailer consistent with irig-106 chapter 10 specifcations. the header contains various data including data packet size, time stamp and header checksum. the trailer is primarily comprised of a data checksum. while the irig-106 standard requires a header and trailer on each data packet, some applications will require data packet size exceeding the ram capacity of the hi-613x device. in this case, the imt may be confgured to disable automatic header and trailer generation, so the entire ram buffer is used for message storage. upon receiving each end-of-packet interrupt, the host offoads the entire block of new message data, which may be appended to a large packet buffer ram, accessible to the host microcontroller. at the appropriate time, the host then generates the required irig-106 packet header and packet trailer. the imt can be confgured to automatically start a new data packet after fnalization of each completed data packet, or the host microcontroller can command the start of the new data packet. in either case, the starting address for the new packet follows the last storage address of the previous packet (even when the last packet was fnalized due to imminent buffer overrun). the device stores packet data in circular buffer fashion, automatically wrapping around to the buffer start address after the last buffer address is written. the host microcontroller is responsible for offoading each data packet in a timely manner to avoid data overwrite by the hi-613x device. one strategy: enable a packet ready interrupt, as well as an n-word warning before full buffer interrupt triggered halfway through the imt ram buffer capacity. the host microcontroller uses these alternating interrupts to pace data buffer offoading, reading a half buffer each time one of the two interrupts occurs. the hi-613x imt is highly fexible. according to the irig-106 standard, the block status word stored for each mil- std-1553 message contains several reserved status bits which always read logic 0. the hi-613x device optionally uses these bits to convey additional status information to the host; the host then resets the reserved bits before including the block status word in the irig-106 data packet. HI-6130, hi-6131
holt integrated circuits 114 14.2. irig-106 bus monitor - data packet format when the hi-613x bus monitor is initialized for imt operation, recorded bus message information is stored in device ram using a data packet format consistent with irig-106 chapter 10. the irig-106 data packet is comprised of three parts: a packet header, a packet body (containing the monitored mil-std-1553 message information) and a packet trailer. the hi-613x imt may be confgured to generate complete data irig-106 packets, including packet header and packet trailer, or may be confgured to generate only the packet body, without packet header and packet trailer. the irig-106 data packet is shown in figure 9 . when the imthtd bit 3 in the imt confguration register 0x0029 is logic 1, the hi-613x stores only the packet body. when the imthtd bit 3 is logic 0, the hi-613x stores a packet header and packet trailer, described on the next pages, in addition to the packet body. HI-6130, hi-6131
holt integrated circuits 115 irig-106 packet header 24 bytes channel specific data,4 bytes irig-106 packet tr aile r 8 bytes increasing memory address packet sync pattern always 0xeb25 packet channel id packet length (bytes) bits 15 -0 data length (bytes) bits 15 -0 sequence number header checksum (16-bit) relative ti me counter ,b its 15-0 relative ti me counter ,b its 31-16 relative ti me counter ,b its 47-32 fille rb its 47 -3 2 0x0000 when needed data checksum (16 bits) message count bits 15 -0 msg count bits 23-16 datat ype v ersion packet flags 0x00 data t ype 0x19 packet length (bytes) bits 31 -1 6 data length (bytes) bits 31 -1 6 reserved 000000 t t fille rb it s1 5- 0 always 0x0000 fille rb it s1 5- 0 0x0000 when needed data packet for message n data packet for message 2 data packet for message 1 message 1 message 2 message 3 message 4 message n packet header packet trailer packet body bit 15 0 ti me ta gb its see ahead for additional details on data packets when register 0x0029 bit 3 equals logic 1, only this message data is recorded. packet header packet trailer figure 9. irig-106 data packet and message storage summary HI-6130, hi-6131
holt integrated circuits 116 14.3. irig-106 packet header description the length of the packet header is fxed at 24 bytes, shown in as twelve 16-bit words. the packet header consists of 10 contiguous felds in the following sequence: 14.3.1. packet sync pattern. a static sync value of 0xeb25 is used for every packet. 14.3.2. channel id. this 2-byte feld contains a value representing the packet channel id. the packet header is generated using the value stored in register 0x002e. 14.3.3. packet length. this 32-bit feld contains a value representing the length of the entire packet. the value indicates the number of bytes in the packet, and is always a multiple of four (bits 1-0 are always 0-0). the packet length includes the packet header, channel specifc data, intra-packet headers, data, filler, and data checksum. (the hi-613x imt does not generate the optional packet secondary header.) 14.3.4. data length. this 32-bit feld contains a value representing the valid data length within the packet, expressed in number of bytes. valid data length includes channel specifc data, intra-packet data headers, intra-packet time stamp(s), and data, but does not include the packet trailer filler and data checksum. 14.3.5. data type version. this 8-bit feld contains a value at or below the release version of the irig-106 standard applied to the data types in the table below. the packet header is generated using the value encoded by bits 11-10 in register 0x0029. the data type value is used in the packet header as shown below. register 0x0029 bits 11-10 data type irig-106 01 0x01 irig-106-04 (original release) 10 0x02 irig-106-05 (default 11 0x03 irig-106-07 00 0x04 irig-106-09 14.3.6. sequence number. this 8-bit feld contains a value representing the packet sequence number for each channel id. this is simply a counter that increments to a maximum count of 0xff, incrementing once for every packet transferred. after master reset, the sequence number starts at 0x00. upon reaching 0xff, the sequence number rolls over to 0x00 and continues counting. 14.3.7. packet flags. this 8-bit feld equals either 0x00 or 0x02, depending on the checksum type selected by bit 1 in register 0x0029. if data HI-6130, hi-6131
holt integrated circuits 117 checksum is disabled, this feld equals 0x00. if 16-bit data checksum is enabled, this feld equals 0x02. although bits 7-2 in this feld always equal logic 0, the encoded signifcance for all eight packet flags is explained here: ? packet secondary header is not present (bit 7) ? packet header 48-bit relative time count used for intra-packet time stamps (bit 6) ? sync error did not occur for relative time count (bit 5) ? data overfow error did not occur (bit 4) ? optional irig-106 packet secondary header is not used (bits 3-2) ? data checksum format: bits 1-0 always equal 00 or 10 00 = data checksum disabled (automatic, when register 0x0029 bit 1 = logic 0) 01 = 8-bit data checksum (option not available) 10 = 16-bit data checksum (automatic, when register 0x0029 bit 1 = logic 1) 11 = 32-bit data checksum (option not available) 14.3.8. data type. this 8-bit feld contains a value representing the type and format of the data. the hi-613x imt always generates a fxed data type value of 0x19, which represents a mil-std-1553b format 1 data packet. 14.3.9. relative time counter. this 48-bit (3-word) feld contains a value representing the 10 mhz relative time counter (rtc). the rtc is derived from an internal clock generator, and remains free running during each data packet recording. the 48-bit value applies to the frst bit of message data in the packet body. 14.3.10. header checksum. this 16-bit (1-word) feld contains the 16-bit arithmetic sum of all 16-bit words in the header, excluding the header checksum word itself. 14.4. irig-106 packet trailer description irig-106 defnes a packet trailer consisting of an optional data checksum, preceded by fller words. the standard requires the overall packet length to be an even number of 16-bit words. the hi-613x imt inserts 0x0000 fller words to meet this requirement. every packet generated by the hi-613x imt has a packet trailer consisting of 2 or 3 fller words (0x0000) followed by the 16-bit data checksum word. bit 1 in register 0x0029 enables/disables automatic generation of a 16-bit data checksum. when auto checksum is disabled, the packet trailer simply consists of 3 or 4 fller words. when the confguration bit is logic 1, the 16-bit checksum is written into the last packet word at packet fnalization. if an 8- or 32-bit data checksum is needed, the host must generate it. irig-106 defnes the data checksum as the arithmetic sum of all of the bytes (8-bit checksum), words (16-bit checksum) or long words (32-bit checksum) in the entire packet, excluding the 24-byte packet header and the data checksum itself. 14.5. irig-106 data packet trailer description the hi-613x imt packet body consists of a 32-bit channel specifc data feld, followed by one or more message data blocks, with separate message data blocks for each monitored mil-std-1553 message. HI-6130, hi-6131
holt integrated circuits 118 14.5.1. channel specifc data. this 32-bit feld occurs once per packet and precedes the packet channel data. the channel specifc data is comprised of the following felds: bits 31-30 bits 29-24 bits 23-0 time tag bits reserved, always 000000 message count bits 31-30 indicate the mil-std-1553 data bit at which intra-packet header time stamp occurs for each message: 00 = time stamp occurs at the last bit of the last word in the message 01 = time stamp occurs at the frst bit of the frst word in the message 10 = time stamp occurs at the last bit of the frst word in the message 11 = reserved, not used bits 23-0 indicate the binary count for the number of mil-std-1553 messages included in the packet. an integral number of complete transaction messages will be in each packet for each monitored mil-std-1553 message, three data felds are stored in the packet body. these are shown in figure 11 , and explained here: 14.5.2. irig-106 intra-packet time stamp. this 64-bit feld contains a 48-bit relative time counter value that marks the relative reception time for the mil- std-1553 message. the high order 16 bits always equal 0x0000. time stamping occurs at the message bit indicated in the channel specifc data. 14.5.3. irig-106 intra-packet data header. this 48-bit feld is comprised of the following sub felds: block status word (bsw). this 16-bit word indicates status for the following mil-std-1553 message and indi - cates mil-std-1553 bus protocol errors. response time word. this 16-bit word contains two 8-bit felds. for all messages except rt-to-rt, the gap1 byte indicates the rt response time. for rt-to-rt messages, the gap1 byte indicates the transmit rt response time, and the gap2 byte indicates the receive rt response time: bits 15-8 bits 7-0 gap2 gap1 for both gap measurements, response time is measured consistently with mil-std-1553 defnition, from the mid-parity zero crossing of the preceding word, to the mid-sync zero crossing of the rt status word. for both, the resolution is 100 ns per lsb, with a maximum time value of 25.5 s. message length word. this 16-bit word indicates the number of bytes in the following message data block, ranging from 2 to 72 bytes, for 1 to 36 stored 16-bit words. 14.5.4. irig-106 message data. this variable length block stores all mil-std-1553 message words in the order received. the number of words stored depends on the mil-std-1553 message type, ranging from 1 word stored (for a broadcast mode code command without data), to 36 words stored for an rt-to-rt message. refer to figure 11 . an irig-106 packet typically contains numerous mil-std-1553 messages, although the standard states the packet must contain at least one message (no HI-6130, hi-6131
holt integrated circuits 119 empty packets). 14.6. imt block status word (bsw) description the irig-106 standard describes a block status word stored within the intra-packet data header for each monitored mil-std-1553 message. this word provides information regarding message status, the bus on which the message occurred, whether errors occurred during the message, and the type of occurring errors. the irig-106 chapter 10 compliant block status word contains eight reserved bits, which the hi-613x imt writes as logic 0: reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reserved reserved 0 le reserved se we 0 reserved rw eo tm reserved reserved rr ige (fe) bid reserved mr reset host access 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 the hi-613x imt offers an extended status reporting option, enabled when bit 2 in register 0x0029 is logic 1. when this option is enabled, all but one of the reserved status bits are used to convey additional status information. although the extended status bits do not comply with the irig-106 chapter 10 standard, the host can reset the 7 normally reserved bits after reading the bsw. if using the imt-generated 16-bit data checksum (enabled when register 0x0029 bits 1:0 equal 1-0), be advised that the tallied checksum value is based on the bsw value that was written into the data packet by the device, at individual mil-std-1553 message completion. the block status word with extended status is defned: imt block status word with extended status bits enabled (not irig-106 chapter 10 compliant) rrgsa 0 bit host access 0 0 0 0 0 0 0 0 0 cwce 0 rrcw2 mr reset 0 le reserved se we 0 sfs rw eo tm reserved gdb rr ige (fe) bid 0 reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 bit no. mnemonic r/w reset function 15 reserved r/w 0 bit 15 is not used in imt mode, always reads logic 0. 14 reserved r/w 0 bit 14 is not used in imt mode, always reads logic 0. 13 bid r/w 0 bus id (bus b / bus a ). bit 13 indicates the bus id for the message. this bit is logic 0 for a message occurring on bus a. this bit is logic 1 for a message occurring on bus b. HI-6130, hi-6131
holt integrated circuits 120 bit no. mnemonic r/w reset function 12 eo r/w 0 error occurred flag. this bit indicates a message error was encountered. this bit is set when one or more of the following conditions are true (logical-or): ? an unfnished message is superseded by another valid command ? bit 10 illegal gap error is set ? bit 9 response timeout is set ? bit 5 length (word count) error is set ? bit 4 sync type error is set ? bit 3 invalid word error is set ? bit 2 rt-rt gap / sync / address error is set ? bit 1 rt-rt command word 2 error is set (except as noted) ? bit 0 command word content error is set (except as noted) three exceptions where register bit 0 or 1 is set without affecting bit 12 state: bit 1 rt-rt command word 2 errors that do not assert bit 12 ? rt-rt transmit command word 2 subaddress feld equals 00000 or 11111 (mode code command indicated) ? rt-rt transmit command word 2 has the same rt address as receive command word 1 bit 0 command word content error that does not assert bit 12 ? undefned receive mode code 0~15 decimal. 11 rr r/w 0 rt-to-rt transfer when logic 1, bit 11 indicates an rt-to-rt message, beginning with two contiguous command words. 10 ige r/w 0 illegal gap error when logic 1, bit 10 indicates an illegal gap occurred on the bus, other than response timeout. the irig-106 standard refers to this bit as format error, having the same defnition. 9 tm r/w 0 response timeout. when logic 1, bit 9 indicates a response timeout occurred. this bit is set if an rt status word associated with this message failed to arrive within the response time interval specifed by bits 15-14 in the mt confguration register 0x0029. for irig-106 compatibility, bits 15-14 in register 0x0029 should be initialized to 00, corresponding to a 14s response time, as de fned by mil-std-1553b (12s bus dead time). HI-6130, hi-6131
holt integrated circuits 121 bit no. mnemonic r/w reset function 8 gdb r/w 0 good data block transfer. only if extended status is enabled bit 8 is set to logic 1 following completion of a valid, error-free message. this bit is reset to logic 0 following completion of a message in which error occurred. if an rt responds to a transmit command with busy status without transmitting the commanded data word(s), this message does not reset the gdb bit. 7 reserved r/w 0 bit 7 is not used in imt mode, always reads logic 0. 6 sfs r/w 0 status flag set only if extended status is enabled bit 6 is logic 1 when a status bit was set in an rt status word response. 5 le r/w 0 length (word count) error bit 5 indicates that the number of data words transmitted by the bc or rt differs from the word count specifed in the command word. an rt status word with the busy bit set will not cause word count error. a transmit command with response timeout will not cause word count error. 4 se r/w 0 sync type error bit 4 is logic 1 to indicate that a bc transmitted data sync with a command word, or a command / status sync occurred with data word, or an rt responded with data sync in its status word and/or command/ status sync in a data word. 3 we r/w 0 invalid word error (we) bit 3 is logic 1 when invalid word error occurred. this includes manchester decoding errors in the sync pattern or word bits, or the wrong number of bits in the word, or parity error. 2 rrgsa r/w 0 rt-to-rt gap/sync/address error (rrgsa) only if extended status is enabled bit 2 is logic 1 if one or more of these rt-rt message conditions occur: ? mt gap check is enabled (bit 12 equals 1 in register 0x0029) and an rt status word is received having a response time less than 4s, per mil-std-1553b (mid-parity to mid-sync). in other words, the bus dead time was less than 2s. ? one of the rts responds with an invalid status word, having a sync error, a manchester encoding error, bit count error and/or parity error ? one of the rt status words contains an rt address that differs from the rt address in the corresponding command word. HI-6130, hi-6131
holt integrated circuits 122 bit no. mnemonic r/w reset function 1 rrcw2 r/w 0 rt-to-rt command word 2 error (rrcw2) only if extended status is enabled bit 1 is logic 1 if an rt-to-rt message occurs (two contiguous command words) with one or more of the following illogical conditions: ? transmit command word 2 t/ r bit equals 0 (receive) ? transmit command word 2 subaddress feld equals 00000 or 11111 (mode command indicated) ? transmit command word 2 has the same rt address as receive command word 1 0 cwce r/w 0 command word content error (cwce) only if extended status is enabled bit 0 is logic 1 if a received command word violates one or more mil-std-1553b requirements: ? a non-mode broadcast transmit command word occurred. (non- mode has 5-bit subaddress feld equal to decimal 1~30) ? a receive mode code command word was received with mode code in the range of 0~15 decimal (undefned) ? a broadcast transmit mode code command occurred having a mode code value for which broadcast is not allowed (mode code = decimal 0, 2, 16, 18 or 19) 14.7. imt message filter table the irig-106 message monitor can select messages for monitoring through the use of a 128-word mt filter table, located at fxed ram address 0x0100. when the table bit corresponding to a new message command word is logic 1, that message is ignored by the monitor. if the table bit is logic 0, that message is recorded. after mr master reset, all mil-std-1553 messages are monitored because the entire table ranging from 0x0100 to 0x017f inclusive is 0x0000. thus every valid command word received on an idle bus marks the start of a new mil-std-1553 message recorded by the monitor. when the table bit corresponding to a new message command word is logic 1, that message is ignored by the monitor. the message filter table is addressed using three felds in the received command word: the 5-bit rt address feld, the t/ r transmit/receive bit and the msb of the 5-bit subaddress feld. this is illustrated in figure 10 . HI-6130, hi-6131
holt integrated circuits 123 bit fields comprising each received command word command sync terminal address ta4:0 subaddress sa4:0 word count (mode code) wc4:0 t/ bit r filter table address p 0 0 1 0 0 0 0 0 0 figure 10. deriving the monitor filter table address from the received command word each rt address from 0 to 31 decimal has four 16-bit table words: two words enable/disable individual receive subaddresses, two more words enable/disable individual transmit subaddresses. the frst four table words apply to subaddress 0 and are illustrated in table 13 . this 4-word pattern repeats for all 32 subaddresses, 0-31 decimal. table 13. imt message filter table filter table addresses 0x017c - 0x017f rt address 31 subaddresses (4 words) filter table addresses 0x0178 - 0x017b rt address 30 subaddresses (4 words) . . . . . . filter table addresses 0x0108 - 0x010b rt address 2 subaddresses (4 words) filter table addresses 0x0104 - 0x0107 rt address 1 subaddresses (4 words) filter table address 0x0103 rt address 0, transmit subaddresses 31 to 16 word bit # 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 transmit sa 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 filter table address 0x0102 rt address 0, transmit subaddresses 15 to 0 word bit # 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 transmit sa 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 filter table address 0x0101 rt address 0, receive subaddresses 31 to 16 word bit # 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 receive sa 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 filter table address 0x0100 rt address 0, receive subaddresses 15 to 0 word bit # 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 receive sa 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 a subaddress message is monitored when the corresponding word bit equals logic 0. the message is not monitored when the bit equals 1. HI-6130, hi-6131
holt integrated circuits 124 non-broadcast message types corresponding broadcast messages 1-32 data w ords: dat an data 1 ......... t ransmittin gr t status w ord 1-32 data w ords: dat an data 1 ......... receiving rt status w ord 1-32 data w ords: dat an data 1 ......... t ransmittin gr t status w ord receiving rt status w ord 1-32 dat aw ords: data n data1 ......... 1-32 dat aw ords: data n data1 ......... mode dat aw ord receiving rt status w ord t ransmittingr t status w ord no broadcast v ersion t ransmit command w ord no broadcast v ersion receive command w ord receive command w ord t ransmit command w ord receive command w ord t ransmi t command w ord receive command w ord t ransmit mode command w ord t ransmittin gr t status w ord mode dat aw ord mode data w ord receive mode command w ord receive mode command w ord rt status w ord tx or rx mode command w ord broadcast tx or rx mode code without data tx or rx mode command w ord these three elements are repeated for each monitored message irig-106 intra-packet ti me stamp, 4w ords message data block 1t o3 6m essage w ords irig-106 intra-packet data header , 3w ords message ti me stamp, bits 15-0 message ti me stamp, bits 31-16 message ti me stamp, bits 47-32 message ti me stamp, bits 63-48 block status w ord see next page message length w ord response ti me w ord increasing memory address message data block stores message words in the order received. number of words stored depends on message type. note 1 note 2 note 3 notes: 1. the message lengt hw ord indicates the number of bytes stored in the message dat ab lock. the range is 2t o7 2 bytes, corresponding t o1t o3 6 16-bit words stored. 2. the response ti me w ord contains two 8-bi tf ields: for al lm essages except rt -to-r t, the gap1 byte indicates th e onlyr t response time. for rt -to-r t, the gap1 bytei ndicates the t ransmit rt response time, and the gap2 byte indicates the receive rt response time. for both, the gap is measured from mid-parity zero-crossing of the preceding word, to them id-sync zero-crossing of the status w ord. the gap time resolutioni s 100ns per lsb, so them aximu mi ndicated gap time is 25. 5. 3. the high order message ti me stampw ord (bits 63~48) is always 0x0000. bits 15 -8 contain gap2 bits 7-0 contain gap1 s rt-to-bc (transmit) command bc-to-rt (receive) command broadcast bc-to-rt (receive) command rt-to-rt command broadcast rt-to-rt command transmit mode code with data receive mode code with data transmit or receive mode code without data broadcase receive mode code with data figure 11. irig-106 data fields and message storage HI-6130, hi-6131
holt integrated circuits 125 15. irig-106 bus monitor (imt) configuration and operation the hi-613x is initialized for irig-106 chapter 10 operation (imt) by resetting bit 0 in the bus monitor confguration register 0x0029 to logic 0. the mil-std-1553 bus monitors that comply with irig-106 produce data packets in a format defned by the irig-106 standard. figure 9 shows the overall data packet structure, comprised of three parts: a packet header, a packet body (containing the monitored mil-std-1553 message information) and a packet trailer. the hi-613x imt may be confgured to generate complete data irig-106 packets, including packet header and packet trailer, or may be confgured to generate only the packet body, without header or trailer. a range of options is offered for confguring the packet header and packet trailer. 15.1. generating complete irig-106 data packets imthtd bit 3 in the mt confguration register 0x0029 is logic 0 the imt generates the packet header and packet trailer after the frst mil-std-1553 message is recorded when starting a new packet. when each new message data packet is added to the packet body, the device updates the packet header and generates a new packet trailer. refer to figure 9 . when one data packet is fnalized and the next data packet begins, the device adjusts the address list pointers so the new packet header starts at the last unwritten buffer address. 15.2. generating only irig-106 packet body (no header or trailer) imthtd bit 3 in the mt confguration register 0x0029 is logic 1 the imt devotes the entire ram buffer for message data packets. for each monitored message, only the intra-packet timestamp, intra-packet data header, and message data block are stored, per figure 11 and the note in figure 9 . when operated in this mode, the ram buffer is fully utilized for message data; the frst intra-packet timestamp occurs at the buffer start address initialized in the imt address list. the host assumes responsibility for generating the irig- 106 packet header, channel specifc data and packet trailer. otherwise, there may be situations when imt packet body structure is simply preferred over smt storage format, in a non-irig application that does not need the header or trailer overhead. when operating in imt mode, mil-std-1553 message data is added to the unfnished data packet until the packet is fnalized. the host can initiate packet fnalization by setting the pktstop bit in the mt confguration register. criteria for automatic packet fnalization can be specifed using customized limits. these host-initialized limits for packet completion are optional, enabled or disabled by confguring limit registers 0x002a through 0x002d. when the applicable limit register contains zero, that criteria for packet fnalization is disabled. the practical maximum value for each of these limits is actually much smaller than limits shown below, as explained in the descriptions for registers 0x002a through 0x002d. ? host-specifed maximum mil-std-1553 message count (1 to 65,535) in register 0x002a ? host-specifed maximum word count (1 to 65,535 words) in register 0x002b ? host-specifed maximum recording time (655.35 ms max, 10 s resolution) in register 0x002c ? host-specifed maximum intermessage gap (655.35 ms max, 10 s resolution) in register 0x002d the data packet ends and packet generation encapsulates the recorded data when the frst of the set data packet limits is reached. an open irig-106 data packet is also fnalized when written packet data frst crosses within 64 words of overrunning buffer space. this criteria, imminent buffer overrun, is mandatory and cannot be disabled. the current data packet is terminated when written packet length is within 64 words of overwriting the current packet start address (maintained HI-6130, hi-6131
holt integrated circuits 126 in address list word 1 by the device). the host initializes a monitor address list in ram to reserve address space for the imt storage buffer and defne buffer utilization interrupt behavior. for imt mode, the 8-word monitor address list is defned as shown in table 14 . table 14. monitor address list for imt mode addr. list name function word 7 packet fill warning interrupt host initialized with a word count value, n, if this interrupt is enabled. if enabled, an interrupt occurs when packet length reaches n words before current packet start address (in word 1) will be overwritten. words 6 ? 5 not used the value in words 5 and 6 is dont care. word 4 last written block status word address maintained by the device. this word is updated by the device each time a block status word is added to the end of the packet for a newly received mil-std-1553 message. the addressed location contains the frst word written for the last message. word 3 buffer address interrupt host initialized with a ram address value if this interrupt is enabled. if enabled, an interrupt occurs when the matching ram address is written. address must be within the range bounded by words 0 and 2. word 2 buffer end address host initialized, defnes monitor buffer upper address boundary. word 1 current packet start address must be host initialized, usually to match buffer start address. updated by device each time a new data packet is opened. this value advances through the address range in circular buffer fashion for successive packets. word 0 buffer start address smt end of message interrupt. successful completion of a mil-std-1553 message, regardless of validity. for purposes of this discussion, it is important to make a distinction between buffer addresses and packet addresses. the buffer address range is fxed and initialized when the host writes address list words 0 and 2. the packet address range is dynamic. the current packet start address must be initialized by the host for the frst data packet; however this value is maintained by the device each time a new packet it started. ? buffer start address and buffer end address defne the imt data storage boundaries. these limits usually do not coincide with stored data packet boundaries, except the frst data packet following device mr reset typically begins at the buffer start address. ? packet start address and packet end address express a smaller address range for storing an imt data packet. because successive data packets are written in circular buffer fashion, there are times when packet start ad - dress approaches the buffer end address. the packet flls the remaining buffer address range and wraps around to continue storing the packet at the buffer start address and beyond. in this case, packet start address is greater than packet end address, but both packet addresses occur between the buffer start and end addresses. ? current packet start address is initialized by the host (typically equal to buffer start address) but is updated by the device each time a data packet is fnalized, and the next data packet has started at the following memory address. ? initialized values for registers 0x002a C 0x002d may result in multiple small packets occurring within the buffer address range. if registers 0x002a through 0x002d all contain zero, data packet fnalization defaults to imminent HI-6130, hi-6131
holt integrated circuits 127 buffer overrun mode. each data packet created will be slightly less than the allocated buffer address range. suc - cessive irig-106 data packets are written in circular buffer fashion. each new data packet starts one word after the fnal word in the previously fnalized data packet. ? if the frst data packet after reset begins at the buffer start address, it will be fnalized and the second data packet will begin before reaching the buffer end address boundary. ? last-written block status word address is updated by the device each time a block status word is added to the end of the packet for a newly received mil-std-1553 message. ? two optional buffer interrupts are offered. when enabled, the buffer address interrupt occurs whenever the matching ram address in the buffer is written. this address is fxed with respect to the buffer start and end ad - dresses. ? when enabled, the packet fill warning interrupt is generated when the packet length reaches a specifed num - ber of words before packet start address overwrite occurs. because packet start address walks through the buffer address range for successive packets, the interrupt logic adjusts the packet fill warning interrupt address automatically. the fll warning number can be any value, i.e. half-way, 8,192 for a 16,384-word buffer. used in conjunction with the packet ready interrupt, this packet half full setting produces alternating interrupts at the half full and full packet conditions. to prevent packet start address overwrite, these two interrupts tell the host when to offoad data, a half packet at a time. in the event that the host is unable to immediately service a packet ready interrupt, no data is lost when the imt is confgured to immediately start a new packet upon completion of the prior packet (i.e., when pktmr bit 7 equals logic 1 in the imt confguration register 0x0029). HI-6130, hi-6131
holt integrated circuits 128 16. registers used by the imt bus monitor in addition to the registers described here, a hi-6131 imt bus monitor also utilizes one or more memory address pointer registers (described in section 9.10 ) for managing spi read/write operations. this comment does not apply for parallel bus interface HI-6130 designs. 16.1. imt bus monitor mt confguration register (0x0029) pktstop mtto0 mtdtv1 mtttb1 mtttb0 mtsrr1 pktmr mthtd mtxmf gchk 0 mtto1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 smt / imt mtsrr0 mtcriw rw mtdtv0 0 csum/8stk w rw mr reset host access bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit no. mnemonic r/w reset function 15 ? 14 mtto1:0 r/w 0 mt time out select. this 2-bit feld selects the monitor no response time-out delay from four available selections. excluding rt-rt commands, the delay is measured from command word mid-parity bit to status word mid-sync. bit 15:14 bus dead time time out (excludes rt-rt) rt-rt time out 00 01 10 11 16s 21s 80s 138s 18s 23s 82s 140s 61s 66s 122s 180s for rt-rt commands, time out delay is measured per figure 8 in the rt validation test plan, sae as4111. that is, from mid-parity of the receive command to mid-sync of the frst received data word. this adds 40s for the embedded transmit command word and transmit-rt status word within this interval. 13 pktstop w 0 mt packet stop. if packet recording is underway when the pktstop bit is set, the imt stops recording then post-processes the packet. if a mil-std-1553 message is underway when pktstop is set, recording continues to message completion. the imt immediately begins recording a new packet. if packet recording is not underway, setting pktstop has no effect. this bit self-resets when written to logic 1. writing logic 0 to this bit has no effect. HI-6130, hi-6131
holt integrated circuits 129 bit no. mnemonic r/w reset function 12 gchk r/w 0 gap check. when this bit equals 1, the imt monitor evaluates inter-message gaps and rt response times for a minimum preceding bus dead time of 2 s. this dead time corresponds to an inter-message gap of 4s, measured per mil-std-1553, from mid-parity zero crossing of the preceding word, to mid-sync zero crossing of the following word. a minimum gap time violation results in a format error in the block status word for the message. when this bit equals 0 (recommended), the monitor does not check for short inter-message gap times. 11 ? 10 mtdtv1:0 r/w 0 imt packet header data type version. this imt setting is only meaningful when mthtd (register bit 3) equals 0, enabling automatic generation of irig-106 data packet header and packet trailer. the irig-106 chapter 10 packet header contains an 8-bit feld data type feld corresponding to the irig-106 version applied to the data. register bits 15-14 specify one of four data type values (0x01 C 0x04) for insertion into the generated packet header: bit 11:10 header data type irig release 00 01 10 11 0x04 0x01 0x02 0x03 irig-106-09 irig-106-04 irig-106-05 (default) irig-106-07 this selection does not affect data encoding, only the 8-bit data type code inserted into the irig-106 packet header. 9 ? 8 mtttb1:0 r/w 0 monitor time tag message bit select. this 2-bit feld selects the bit within the mil-std-1553 message where time stamp occurs. time stamp occurs at mid-bit transition: bit 9:8 time tag event 00 01 10 11 last bit of last word in message first bit of first (command) word in message last bit of first (command) word in message time tag disabled, stores time tag = 0 for options 00 and 10, the last bit precedes the words parity bit. for option 01, the first bit occurs 0.5s after command sync. while first word generally denotes a command word, message recording can begin with a data word when register bit 5 equals 1. HI-6130, hi-6131
holt integrated circuits 130 bit no. mnemonic r/w reset function 7 pktmr r/w 0 imt packet timer mode. when the pktmr bit is logic 0, the packet timer resets when the imt is enabled. the packet timer then starts counting when the next mil- std-1553 message begins, at detection of the frst valid command word (or alternate start-record requirement selected by bits 6-5 below.) if the pktmr bit is logic 1 when the imt is enabled, the packet timer resets then immediately starts when the imt is enabled. in this mode, whenever a data packet is fnalized, the packet timer resets then restarts, and new packet recording is immediately started. if enabled, a pktrdy (packet-ready) interrupt is generated for the host, at packet completion. 6 ? 5 mtsrr1:0 r/w 0 imt start-record requirement 1:0. when register bits 6-5 equal 00, the imt starts recording a new mil-std-1553 message when a properly encoded, complete mil- std-1553 word with command sync is decoded: the command sync is followed by 16 properly encoded data bits plus a 17th parity bit expressing odd parity. no data is recorded until this condition is met. this is the usual setting. (default setting) when register bits 6-5 equal 01, the imt starts recording a new mil-std-1553 message when a properly encoded, complete mil- std-1553 word with command sync or data sync is decoded. the properly encoded command sync (or data sync) is followed by 16 properly encoded data bits plus a 17th parity bit expressing odd parity. if recording begins with data sync, the sync error fag will be set in the block status word. when register bits 6-5 equal 10, the imt starts recording a new mil- std-1553 message upon detection of a properly encoded command sync with two contiguous data bits . if the properly encoded command sync with two contiguous data bits does not result in a valid command word, the invalid word error is set in the block status word. this selection begins recording for complete mil-std-1553 command words as well as for command word fragments, or command words with bad parity. under some circumstances, this record option might be helpful for debugging mil-std-1553 communication failure. when register bits 6-5 equal 11, the imt starts recording new bus activity upon detection of any properly encoded sync (command or data) with two contiguous data bits . this selection begins recording for complete mil-std-1553 command or data words as well as for word fragments, or words with bad parity. if the properly encoded sync with two contiguous data bits does not result in a valid manchester ii word, the invalid word error is set in the block status word. if recording begins with data sync, the sync error fag will be set in the block status word. under some circumstances, this record option might be helpful for debugging mil-std-1553 communication failure. HI-6130, hi-6131
holt integrated circuits 131 bit no. mnemonic r/w reset function 4 mtcriw r/w 0 imt continue recording after invalid word. when bit 4 equals 0, the imt stops recording an incomplete message when an invalid mil-std-1553 word is decoded. the invalid word is not stored, and the imt awaits word detection per register bits 6-5 before the next mil-std-1553 message is recorded. (default) when bit 4 equals 1, the mt continues recording an incomplete message when an invalid mil-std-1553 word is decoded. the invalid word is stored and the imt continues monitoring the message until completion or time-out occurs. 3 imthtd r/w 0 imt (data packet) header and trailer disabled. when bit 3 equals 0, the imt reserves space for an irig-106 packet header and packet trailer in the ram buffer assigned in the mt address list. the packet header and packet trailer are automatically generated by the device at packet fnalization and stored in the assigned buf fer. (default) when bit 3 equals 1, the imt generates only the irig-106 packet body, stored in the assigned buffer. the full buffer address range is used for message storage. 2 mtxmf r/w 0 imt extended message flag enable. when register bit 2 equals 0, the recorded status/error fags are limited to the defned bits in the irig-106 block status word. see section 14.6 . when register bit 2 equals 1, expanded status/error fags are enabled, occupying reserved bit positions in the irig-106 block status word. 1 imtcksm r/w 0 imt checksum enable this imt setting is only meaningful when imthtd (register bit 3) equals 0, enabling automatic generation of irig-106 data packet header and packet trailer. when register bit 1 equals 1, a 16-bit checksum is tallied for the data packet body, and stored in the packet trailer at packet fnalization. when register bit 1 equals 0, no checksum is tallied for the data packet body. 0 smt / imt r/w 0 select simple monitor terminal (smt) or irig-106 monitor terminal (imt). this register bit must equal logic 0 for imt operation. when this bit is zero, the bus monitor operates in imt irig-106 mode with 48-bit time tag counter resolution. HI-6130, hi-6131
holt integrated circuits 132 16.2. imt bus monitor address list start address register (0x002f) rw mr reset host access bit 15 14 13 12 11 10 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 0 9 8 7 6 5 4 3 2 1 0 register value msb lsb this 16-bit register is read-write and is fully maintained by the host. after mr pin master reset, this register is initialized with 0x00b0, the default base address of the monitor address table in device ram. the host can overwrite the default base address. this register is not affected by mt soft reset, when the mtreset bit is asserted in the master status and reset register, 0x0001. the address list for imt monitor is shown in table 14 on page 126 . 16.3. imt bus monitor next message storage pointer (0x0030) r mr reset host access bit 15 14 13 12 11 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 8 7 6 5 4 3 2 1 0 register value msb lsb this 16-bit register is read-only and is updated by the imt after completion of a monitored mil-std-1553 message. this register is cleared after nmr pin master reset or by mt soft reset, when the mtreset bit is asserted in the master status and reset register, 0x0001. this register contains the ram address for the next-written block status word, for the next mil-std-1553 message. after the frst post-reset message is logged, this register mirrors the value contained in the current packet start address, word 1 in the monitor address list (see table 14 on page 126 ). the imt logic only updates this next message address register after message completion. therefore, after reset, this register does not contain a valid pointer address until the next valid message is completed. if the read value equals zero, the next message address equals the buffer start address. 16.4. imt bus monitor last message buffer address (0x0031) r mr reset host access bit 15 14 13 12 11 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 8 7 6 5 4 3 2 1 0 register value msb lsb this 16-bit register is read-only and is updated by the imt upon completion of a monitored mil-std-1553 message. this register is cleared after nmr pin master reset or by mt soft reset, when the mtreset bit is asserted in the master status and reset register, 0x0001. this register contains the block status word address in ram for the last completed mil-std-1553 message. HI-6130, hi-6131
holt integrated circuits 133 16.5. imt packet maximum message count register (0x002a) rw mr reset host access bit 15 14 13 12 11 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 8 7 6 5 4 3 2 1 0 register value msb lsb this 16-bit register is read-write and is maintained by the host. this register is cleared after mr pin master reset but is not affected by mt soft reset, when the mtreset bit is asserted in the master status and reset register, 0x0001. this register only applies when the monitor is confgured for irig-106 chapter 10 operational mode , which is when imt bit 0 is initialized to logic 0 in the mt confguration register 0x0029. in this mode, monitored message data is stored in data packets in the monitor buffer. the hi-613x imt fnalizes the unfnished packet when the number of mil-std-1553 messages in the packet reaches the value in this register. if register value is zero, this criteria is not used for determination of end-of-packet. 16.5.1. practical irig-106 packet message count considerations irig-106 chapter 10 stipulates a maximum allowable time interval of 100 ms for any data packet. the maximum number of packet messages occurs when the bc continuously transmits back-to-back broadcast mode code commands without data, each with the minimal allowable intermessage gap of 4 s, yielding 2 s dead time between commands. this results in repeating message transmission every 22 s. therefore the maximum packet message count is (100 ms / 22 s) or 4,545 messages occurring in the maximum allowed 100 ms packet interval. therefore, for strict compliance with irig-106, the maximum attainable packet message count is 4,545 decimal. the hi-613x device can be confgured to record packet times exceeding the irig-106 limit. without regard for maximum packet time allowed by irig-106, the maximum message count governed by hi-613x ram capacity is a lower value. if the hi-613x is confgured as imt only, the maximum contiguous ram space is 0x7fff C 0x01bf = 0x7e40 = 32,320 words. maximum message storage space occurs when the hi-613x imt is confgured to provide the data packet body, without packet header or trailer. 14 words are used for packet header, leaving 32,306 words for messages. if the bc continuously transmits back-to-back broadcast mode code commands without data, each message consumes 8 words of buffer space. this unlikely repeating message sequence yields the highest packet possible message count for a ram-limited hi-613x monitor, which is 32,306 / 8 = 4,038 messages. transmit and receive subaddress commands typically require far more than 8 stored words per mil-std-1553 message, so normal bus traffc will probably fll the imt buffer far in advance of 4,000 messages. 16.6. imt packet maximum 1553 word count register (0x002b) rw mr reset host access bit 15 14 13 12 11 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 8 7 6 5 4 3 2 1 0 register value msb lsb this 16-bit register is read-write and is maintained by the host. this register is cleared after mr pin master reset but is not affected by mt soft reset, when the mtreset bit is asserted in the master status and reset register, 0x0001. this register only applies when the monitor is confgured for irig-106 chapter 10 operational mode , which is when imt bit 0 is initialized to logic 0 in the mt confguration register 0x0029. in this mode, monitored message data is stored in data packets in the monitor buffer. the hi-613x imt fnalizes the unfnished packet when the number of 16-bit mil-std-1553 message words in the packet reaches the value in this register. this word count is comprised of bc command, rt status and message data words. it excludes irig-106 header and trailer (if used) and message block data words and time stamp words. if the register value is zero, this register is not used for determination of end- HI-6130, hi-6131
holt integrated circuits 134 of-packet. 16.6.1. practical irig-106 packet word count considerations irig-106 chapter 10 stipulates a maximum allowable time interval of 100 ms for any data packet. the maximum number of mil-std-1553 packet words occurs when the bc continuously transmits back-to-back 32 data word broadcast receive with 32 data words, each with the minimal allowable intermessage gap of 4 s, yielding 2 s dead time between commands. this results in repeating message transmission every 662 s. therefore (100 ms / 662 s) or 151.1 such messages occur in the maximum allowed 100 ms packet interval. therefore, for strict compliance with irig-106, the maximum number of mil-std-1553 words in a maximum duration 100 ms irig-106 packet is 151.1 messages x 33 words/message = 4,985 words. the hi-613x permits longer packet recording times than 100 ms. the maximum contiguous ram space in the device ram for an imt buffer is about 32,200 words, achievable when the device is confgured as imt only (no concurrent bc or rts). to achieve even larger packets, the host can accumulate packet body increments read from hi-613x ram in a separate, larger ram. the hi-613x would probably be confgured without automatic packet header and trailer generation, to record message data in the format shown in figure 7 irig-106 message data storage on page 67. upon completion of each large packet (accumulated from multiple hi-613x sub-packets), the host generates the packet header, channel specifc data and packet trailer for the accumulated packet data body. 16.7. imt maximum packet time register (0x002c) rw mr reset host access bit 15 14 13 12 11 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 8 7 6 5 4 3 2 1 0 register value msb lsb this 16-bit register is read-write and is maintained by the host. this register is cleared after mr pin master reset but is not affected by mt soft reset, when the mtreset bit is asserted in the master status and reset register, 0x0001. this register only applies when the monitor is confgured for irig-106 chapter 10 operational mode , which is when imt bit 0 is initialized to logic 0 in the mt confguration register 0x0029. in this mode, monitored message data is stored in data packets in the monitor buffer. the hi-613x imt fnalizes the unfnished packet if the packet data recording time (measured in 10 s increments) reaches the value in this register. if register value is zero, the register is not used for determination of end-of-packet. 16.7.1. practical irig-106 packet time considerations irig-106 chapter 10 stipulates a maximum packet time of 100 ms. therefore, for strict compliance with the standard, the maximum count contained in this register would be (100 ms / 10 s) = 10,000 decimal. the hi-613x device logic allows a maximum packet time greater than 100 ms. if the register contains 0xffff, the maximum packet time is 655.35 ms. 16.8. imt packet maximum gap time register (0x002d) rw mr reset host access bit 15 14 13 12 11 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 8 7 6 5 4 3 2 1 0 register value msb lsb HI-6130, hi-6131
holt integrated circuits 135 this 16-bit register is read-write and is maintained by the host. this register is cleared after mr pin master reset but is not affected by mt soft reset, when the mtreset bit is asserted in the master status and reset register, 0x0001. this register only applies when the monitor is confgured for irig-106 chapter 10 operational mode , which is when imt bit 0 is initialized to logic 0 in the mt confguration register 0x0029. in this mode, monitored message data is stored in data packets in the monitor buffer. if the elapsed time between successive mil-std-1553 words (measured in 10 s increments) reaches the value in this register, the hi-613x imt fnalizes an unfnished packet. the maximum time interval is 655.35ms. the measured interval restarts after each manchester word, and ends with gap time-out, or detection of the next-occurring valid manchester word on either bus. under normal circumstances, this register is used for determination of gaps between mil-std-1553 messages, however message fragments containing valid manchester words also preempt time-out and restart the timer. 16.8.1. practical irig-106 maximum gap time considerations word validation occurs about 3us after manchester word completion. when the programmed value in this register is n, the in-process packet will fnalize at (10n + 3) s, unless a valid manchester word started before the maximum bus dead time of (n-2) x 10 s. when the stored register value is zero, this register is not used for end-of-packet determination. example: this register contains 20 decimal. the resultant maximum allowed bus dead time between manchester words is 180 s. when gap time exceeds this limit, packet fnalization occurs at 203 s, and (if enabled) mt interrupts occur for packet ready and maximum gap time. a valid manchester word starting after 180 s is not included the dolhgsdfnhwexwpdehwhuvwruglwhiroorlsdfnhwhelwvlwh07rxudwlr5hlvwhuhtxdo 0-0 or 0-1. 16.9. imt packet header channel id register (0x002e) rw mr reset host access bit 15 14 13 12 11 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 8 7 6 5 4 3 2 1 0 register value msb lsb this 16-bit register is read-write and is maintained by the host. this register is cleared after mr pin master reset but is not affected by mt soft reset, when the mtreset bit is asserted in the master status and reset register, 0x0001. this register is only used when the mt is confgured for irig-106 chapter 10 operational mode, with automatic packet header and packet trailer generation. that is, when imt bit 0 is initialized to logic 0, and imthtd bit 3 is initialized to logic 1 in the mt confguration register 0x0029. the irig-106 chapter 10 packet header includes a 16-bit channel id. the value contained in this register is used for the channel id feld, when generating the packet header. the host must load a nonzero value into this register during initialization because channel id of 0x0000 is reserved for computer-generated data packets. HI-6130, hi-6131
holt integrated circuits 136 16.10. imt monitor time tag count low register (0x003a) r mr reset host access bit 15 14 13 12 11 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 8 7 6 5 4 3 2 1 0 register value msb lsb 16.11. imt monitor time tag count mid register (0x003b) r mr reset host access bit 15 14 13 12 11 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 8 7 6 5 4 3 2 1 0 register value msb lsb 16.12. imt monitor time tag count high register (0x003c) r mr reset host access bit 15 14 13 12 11 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 8 7 6 5 4 3 2 1 0 register value msb lsb the imt bus monitor always uses a 48-bit time base. the current time base value is refected in these three 16-bit registers. these registers are read-only and are cleared after mr pin master reset. count bits 47-32 reside in register 0x003c, count bits 31-16 reside in register 0x003b while register 0x003a contains bits 15-0. the host cannot directly write into these registers, but can otherwise control the mt time tag count. by writing bits 15-14 in the time tag counter confguration register 0x0039, the host can: ? clear the 48-bit time tag count to zero (by loading three 0x0000 values) ? simultaneously copy the 3-register time value into the three imt time tag utility registers ? simultaneously load the value contained in the three imt time tag utility registers into the imt time tag count registers. finally, three imt time tag match registers provide capability for generating a host interrupt when the time tag count reaches any predetermined 48-bit value. for further information, refer to the description of the time tag counter confguration register 0x0039. 16.13. imt time tag utility low register (0x003d) rw mr reset host access bit 15 14 13 12 11 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 8 7 6 5 4 3 2 1 0 register value msb lsb HI-6130, hi-6131
holt integrated circuits 137 16.14. imt time tag utility mid register (0x003e) rw mr reset host access bit 15 14 13 12 11 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 8 7 6 5 4 3 2 1 0 register value msb lsb 16.15. imt time tag utility high register (0x003f) rw mr reset host access bit 15 14 13 12 11 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 8 7 6 5 4 3 2 1 0 register value msb lsb these multifunction registers are read-write and are cleared after mr pin master reset. this utility register triplet is used for simultaneously copying a 48-bit value into the three corresponding imt time tag count registers. these registers are also used for simultaneously capturing the 48-bit value from the imt time tag count registers. please refer to the description for bits 15-14 in the time tag counter confguration register 0x0039 in section 9.9 . 16.15.1. loading a 48-bit value into the three 16-bit smt time tag count registers when loading or clearing time tag count, the 16-bit value in utility register 0x003d is copied into smt time tag coun - ter register 0x003a. simultaneously, count bits 47-17 and count bits 31-16 are copied from time tag utility registers 0x003f and 0x003e into smt time tag counter registers 0x003c and 0x003b. 16.15.2. capturing a 48-bit value from the three 16-bit smt time tag count registers when capturing time tag count, the 16-bit value in smt time tag count register 0x003a is copied into time tag utility register 0x003d. simultaneously, count bits 47-17 and count bits 31-16 in smt time tag count registers 0x003c and 0x003b are copied into time tag utility registers 0x003f and 0x003e respectively. 16.16. imt time tag match low register (0x0040) rw mr reset host access bit 15 14 13 12 11 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 8 7 6 5 4 3 2 1 0 register value msb lsb 16.17. imt time tag match mid register (0x0041) rw mr reset host access bit 15 14 13 12 11 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 8 7 6 5 4 3 2 1 0 register value msb lsb HI-6130, hi-6131
holt integrated circuits 138 16.18. imt time tag match high register (0x0042) rw mr reset host access bit 15 14 13 12 11 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 8 7 6 5 4 3 2 1 0 register value msb lsb these registers are read-write and are cleared after mr pin master reset. when the mtttm bit 6 is logic 1 in the hardware interrupt enable register 0x000f, an interrupt occurs when the value stored in this register triplet matches the 48-bit value in the imt time tag count registers. please refer to the description for mtttm bit 6 in the hardware interrupt registers described in section 9.7 . HI-6130, hi-6131
holt integrated circuits 139 16.19. imt bus monitor interrupt registers and their use section 9.4 on page 36 through section 9.6 describe how the host uses three hardware interrupt registers, the interrupt log buffer and the interrupt count & log address register to manage interrupts. when the imt is enabled, three additional registers are dedicated to imt interrupts. comparable to the hardware interrupt register triplet, the imt has ? an imt interrupt enable register to enable and disable interrupts ? an imt pending interrupt register to capture the occurrence of enabled interrupts ? an imt interrupt output enable register to enable irq output to host, for pending enabled interrupts each individual bit in all three registers is mapped to the same interrupt-causing event when the corresponding interrupt condition is enabled. numerous interrupt options are available for the imt. at initialization, bits are set in the imt interrupt enable register to identify the interrupt-causing events for the imt which are heeded by the hi-613x. most imt applications only use a subset of available imt interrupt options. interrupt-causing events are ignored when their corresponding bits are reset in the imt interrupt enable register. setting an interrupt enable register bit from 0 to 1 does not trigger interrupt recognition for events that occurred while the bit was zero. whenever an imt interrupt event occurs (and the corresponding bit is already set in the imt interrupt enable register), these actions occur: ? the interrupt log buffer is updated. ? a bit corresponding to the interrupt type is set in the imt pending interrupt register. the type bit is logically-ored with the preexisting register value, retaining bits for prior, unserviced imt interrupts. ? mt interrupt pending (mtip) bit 1 used by smt or imt is set in the hardware pending interrupt register. the mtip bit is logically-ored with the preexisting register value, retaining bits for unserviced hardware interrupts and the preexisting status of the bcip and rtip (bus controller and rt) interrupt pending bits. ? if the matching bit is already set in the imt interrupt output enable register, an irq output occurs. if the matching bit in the imt interrupt output enable register was not already set (i.e., low priority polled interrupt), the host can poll the imt pending interrupt register to detect the occurrence of imt interrupts, indicated by non-zero value. reading the imt pending interrupt register automatically clears it to 0x0000. a single irq host interrupt output signal is shared by all enabled interrupt conditions having bits set in the four interrupt output enable registers (hardware, bc, rt and smt or imt). multiple interrupt-causing events can occur simultaneously, so single or simultaneous interrupt events can assert the irq host interrupt output. when the host receives an irq signal from the device, it identifes the event(s) that triggered the interrupt. section 9.4 describes two methods for identifying the interrupt source(s). one scheme uses the three low order bits in the hardware pending interrupt register to indicate when bc, rt, smt and/or imt interrupts occur. when mt interrupt pending (mtip) bit 1 used by smt or imt is set in the hardware pending interrupt register, the imt pending interrupt register contains a nonzero value and may be read next to identify the specifc imt interrupt event(s). or, the host can directly interrogate the interrupt count & log address register, followed by the interrupt log buffer. data sheet section 9.4 has a detailed description. HI-6130, hi-6131
holt integrated circuits 140 16.19.1. imt bus monitor interrupt enable register (0x0011) maxmsgs hpstop irigovf pktrdy reserved pktfw bufmat reserved maxgap 0 maxtime 15 0 0 0 0 0 0 0 0 reserved rw maxwrds 0 reserved 0 r reserved 0 reserved reserved mr reset host access bit 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 16.19.2. imt bus monitor pending interrupt register (0x0008) maxmsgs hpstop irigovf pktrdy reserved pktfw bufmat reserved maxgap 0 maxtime 15 0 0 0 0 0 0 0 0 reserved maxwrds 0 reserved 0 reserved 0 reserved reserved mr reset host access bit 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 r 16.19.3. imt bus monitor interrupt output enable register (0x0015) maxmsgs hpstop irigovf pktrdy reserved pktfw bufmat reserved maxgap 0 maxtime 15 0 0 0 0 0 0 0 0 reserved rw maxwrds 0 reserved 0 r reserved 0 reserved reserved mr reset host access bit 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 these three registers govern imt interrupt behavior: the imt interrupt enable register, the imt pending interrupt register and the imt interrupt output enable register. when a bit is set in the imt interrupt enable register, the corresponding imt interrupt is enabled. when a bit is reset in this register, the corresponding interrupt event is unconditionally disregarded. setting a register bit from 0 to 1 does not trigger interrupt recognition for events that occurred while the bit was zero. when an enabled imt interrupt event occurs, the corresponding bit is set in the imt pending interrupt register and the interrupt log buffer is updated. to simplify interrupt decoding, mtip bit 1 in the hardware pending interrupt register is also set whenever one or more bits are set in the imt pending interrupt register. if the corresponding bit is already set in the imt interrupt output enable register, the irq output pin is asserted at pending interrupt register assertion. the imt interrupt output enable register establishes two priority levels: high priority interrupts generate an irq output while low priority interrupts do not. both priority levels update the imt pending interrupt register and the interrupt log buffer. the host detects low priority (masked) interrupts by polling imt pending interrupt register. the table below frst describes the common bits 15-3 in all three imt interrupt registers and then describes register- to-register differences for bits 2-0. HI-6130, hi-6131
holt integrated circuits 141 bit no. mnemonic function 15 irigovf irig-106 buffer overfow. since start-of-packet, data recording got within 64 words of overwriting the packet start address. the in-process packet terminated at end-of-message. next message begins next packet. 14 maxwrds irig-106 maximum mil-std-1553 word count interrupt. the in-process packet terminated at end-of-message when the number of mil- std-1553 message words recorded in the packet attained the maximum word count stored in the mt packet maximum mil-std-1553 word count register at address 0x002b. 13 maxmsgs irig-106 maximum message count interrupt. the in-process packet terminated at end-of-message when the number of recorded mil-std-1553 messages equals the maximum message count stored in the imt packet maximum message count register at address 0x002a. 12 maxgap irig-106 maximum gap time exceeded interrupt. the in-process packet terminated when the bus monitor encountered a mil-std-1553 message gap interval exceeding the maximum gap time stored in the mt packet maximum gap time register at address 0x002d. 11 maxtime irig-106 maximum recording time exceeded interrupt. the in-process packet terminated when the bus monitor reached the maximum packet time stored in the mt maximum packet time register at address 0x002c. when timeout occurs, packet fnalization occurs after completion of an unfnished message. 10 hpstop host packet stop interrupt. the host asserted the pkstop bit in the mt confguration register to stop the bus monitor. recording stopped after in-process message completion. 9 pktrdy packet ready interrupt. above register bits 15-10 are logically ored to derive the state of this bit. 8 reserved this bit is not used in imt monitor mode. it should be initialized logic 0 in the imt interrupt enable register. 7 reserved this bit is not used in imt monitor mode. it should be initialized logic 0 in the imt interrupt enable register. 6 bufmat buffer address match interrupt. the buffer pointer value has reached the interrupt address in word 3 of the imt address list. 5 pktfw packet fill warning interrupt. host previously initialized word 7 in the imt address list with a word count value, n. the current buffer pointer address has reached n words before overwriting the current packet start address stored in word 1 of the imt address list. 4 reserved this bit is not used in imt monitor mode. it should be initialized logic 0 in the imt interrupt enable register. 3 reserved this bit is not used in imt monitor mode. it should be initialized logic 0 in the imt interrupt enable register. HI-6130, hi-6131
holt integrated circuits 142 bit no. mnemonic function 2 ? 0 reserved bits 2-0 cannot be written, and read back 000. HI-6130, hi-6131
holt integrated circuits 143 17. single or dual remote terminal(s) ? overview the hi-613x can operate as one or two autonomous mil-std-1553 remote terminals, requiring minimal host support. when a single remote terminal (rt) is enabled, its confguration and operation is nearly identical to the holt hi-612x integrated circuit. when two rts are enabled, they operate simultaneously and independently, with the full fexibility of the holt hi-612x remote terminal architecture. designated as rt1 and rt2, the confguration registers for the two terminals are completely duplicated, although certain (i.e., interrupt management) registers are shared between the two rts. each terminal has its own descriptor table, command illegalization table and host interrupt confguration. the discrete input / output pins for the two remote terminals are completely duplicated. the following signal pins are provided for remote terminals rt1 and rt2: ? rt1 and rt2 terminal address 4 - 0 input pins ? rt1 and rt2 terminal address parity input pins ? rt1 and rt2 (address) lock input pins ? rt1 and rt2 enable input pins ? rt1 and rt2 subsystem fail input pins ? rt1 and rt2 mode code 8 (reset remote terminal) output pins by writing the master status and reset register, remote terminals rt1 and rt2 can be independently reset using soft reset. either or both rts can be confgured to automatically assert soft reset when a valid reset remote terminal mode code command is received. in this confguration, the serial auto-initialization eeprom should already be programmed with the desired attributes for the two terminals. when a broadcast reset remote terminal mode command is received, rt1 and rt2 perform soft reset independently, although the read-from-eeprom time interval is doubled. in this section of the data sheet, the remote terminal registers are described frst, followed by the details for confguring and operating one or both rts. HI-6130, hi-6131
holt integrated circuits 144 18. registers used by remote terminals rt1 and rt2 in addition to the registers described here, hi-6131 remote terminals rt1 and rt2 also utilize one or more memory address pointer registers (described in section 9.10 ) for managing spi read/write operations. this comment does not apply for parallel bus interface HI-6130 designs. 18.1. remote terminal 1 (rt1) confguration register (0x0017) remote terminal 2 (rt2) confguration register (0x0020) rtinha rtto0 bcstinv umcinv notice2 trxdb smcp mc17op1 mc17op0 rtinhb 0 rtto1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 mc8opt altbitw autobsd rw dbcena 0 mc16opt mr reset host access bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit no. mnemonic r/w reset function 15 ? 14 rtto1:0 r/w 0 rt-rt time out select. this 2-bit feld selects the no response time-out delay for rt-to-rt receive commands from four available selections: bit 15:14 bus dead time rt-rt time out 00 01 10 11 15s 20s 58s 138s 57s 62s 100s 180s for rt-rt commands, time out delay is measured per figure 8 in the rt validation test plan, sae as4111. that is, from mid-parity of the receive command to mid-sync of the frst received data word. this interval includes 20s each for the embedded transmit command word and transmit-rt status word within this span. 13 rtinha r/w 0 rt bus a inhibit. if this bit is logic 1, bus a for this rt is inhibited, as defned by the bsdtxo bit in register 0. the bsdtxo bit offers two options: inhibit transmit and receive, or inhibit only transmit. setting the rtinha bit inhibits bus a for just this rt, while allowing normal bus a operation by the bc or the other rt. note: if this bit is logic 0, bus a is not inhibited here but its operation may otherwise be globally inhibited by logic 1 at the txinha pin, or logic 1 at the txinha bit in the master status & reset register. HI-6130, hi-6131
holt integrated circuits 145 bit no. mnemonic r/w reset function 12 rtinhb r/w 0 rt1 bus b inhibit. if this bit is logic 1, bus b for this rt is inhibited, as defned by the bsdtxo bit in register 0. the bsdtxo bit offers two options: inhibit transmit and receive, or inhibit only transmit. setting the rtinhb bit inhibits bus b for just this rt, while allowing normal bus b operation by the bc or the other rt. note: if this bit is logic 0, bus b is not inhibited here for this rt but its operation may otherwise be globally inhibited by logic 1 at the txinhb pin, or logic 1 at the txinhb bit in the master status & reset register. 11 bcstinv r/w 0 broadcast commands invalid. if this bit is high, commands addressed to rt address 31 are treated as invalid: there is no terminal recognition of commands to rt address 31; there is no rt command response, and no status updating for the beneft of following transmit status or transmit last command mode commands. if this bit is low, commands addressed to rt address 31 are treated as valid broadcast commands. 10 dbcena r/w 0 dynamic bus control enable. when this bit is logic 1, this rt accepts bus control after receiving a valid legal dynamic bus control mode command. the rt stex bit in the master confguration register resets to 0 and the bcstrt bit in the master confguration register is set to logic 1. if dynamic bus control is allowed, the bcena input pin and register bit in the master confguration register must both be logic 1, and the bus controller should be fully initialized in advance to permit immediate operation. when this bit is logic 0, the host must perform all actions necessary to change from rt to bus controller mode. typically the rt descriptor table is confgured to generate an iwa interrupt to alert the host upon receiving a valid legal dynamic bus control mode code command, mc0. 9 umcinv r/w 0 undefned mode codes invalid. this bit determines whether the rt treats undefned mode code commands as valid (default) or invalid commands. this bit applies only to the following undefned mode code commands: ? mode codes 0 through 15 with t/r bit = 0 ? mode codes16, 18 and19 with t/r bit = 0 ? mode codes 17, 20 and 21 with t/r bit = 1 if this bit is low (default state after nmr pin reset) undefned mode code commands are considered valid, and rt response is based on individual mode command settings in the illegalization table: if mode command is legal, the rt responds in form and updates status. if a mode command is illegal, the rt asserts message error status and (if non-broadcast) transmits only its status word without associated data word. if this bit is high, undefned mode code commands are treated as invalid: there is no rt recognition of an invalid command, no rt command response, and no status updating for the beneft of following transmit status or transmit last command mode commands. HI-6130, hi-6131
holt integrated circuits 146 bit no. mnemonic r/w reset function 8 notice2 r/w 0 notice 2 broadcast data storage. if this bit is high, the terminal stores data associated with broadcast commands separately from data associated with non-broadcast commands to meet the requirements of mil-std-1553b notice 2. if this bit is low, broadcast command data is stored in the same buffer with data from non-broadcast commands. 7 smcp r/w 0 simplifed mode command processing. when this bit is asserted, the respective remote terminal rt1 or rt2 applies simplifed mode command processing for all valid mode code commands, as described in section 21.5 on page 212 . 6 trxdb r/w 0 temporary receive data buffer. when this bit is asserted, the respective remote terminal rt1 or rt2 enables a temporary receive data buffer used during receive commands. see section 19.3 on page 168 . when this bit is asserted, rt1 or rt2 stores received data words in a 32-word data buffer during message processing. only after error-free message completion, are the buffered words are written into the data buffer memory assigned to the specifc subaddress in the rt1 or rt2 descriptor table. this bit should only be modifed when rt1stex and rt2stex bits are low in master confguration register 0x0000 (see section 9.1 on page 29 ). changing the trxdb bit when the rt1stex or rt2stex confguration bit is logic-1 causes unpredictable results. 5 altbitw r/w 0 alternate bit word enable. when this bit is logic 0, the respective remote terminal rt1 or rt2 responds to a transmit bit word mode command (mc19) by sending the word stored in its built-in test word register. the built-in test word register for rt1 resides at address 0x001e. the built-in test word register for rt2 is at address 0x0027. when this bit is logic 1, the respective remote terminal rt1 or rt2 responds to a transmit bit word mode command (mc19) by sending the word stored in its alternate built-in test word register. the alternate built-in test word register for rt1 resides at address 0x001f. the alternate built-in test word register for rt2 is at address 0x0028. using an alternate built-in test word register allow the user to fully defne the bit word, while the default built-in test word register locations contain several predefned, device-controlled status bits. HI-6130, hi-6131
holt integrated circuits 147 bit no. mnemonic r/w reset function 4 autobsd r/w 0 automatic bus shutdown enable. the bus controller exercises shutdown control over remote terminal connections to the inactive mil-std-1553 bus using the transmitter shutdown (mc4) or selected transmitter shutdown (mc20 decimal) mode code commands. these apply only to the inactive bus. the rt cannot shutdown the bus where the command is received. when the inactive bus transmitter is shutdown, the hi-613x device inhibits further transmission affected on that bus for the affected rt(s). once shutdown, the transmitter can be reactivated by (a) an override transmitter shutdown (mc5) mode command, (b) an override selected transmitter shutdown (mc21 decimal) mode command, (c) a reset remote terminal (mc8) mode command, (d) asserting hardware mr master reset input pin or (e) software reset initiated by setting the rt1reset or rt2reset bit in the master status and reset register 0x0001. with the autobsd bit reset, the device only transmits rt status upon receiving mc4, mc5, mc20 or mc21. the host must perform bus shutdown and override duties by asserting control of the txinha and txinhb bits in the master confguration register, or by controlling the input pins with the same function. with autobsd bit set, upon receiving mc4 (or mc20 with data word matching bus select criteria), the device automatically fulflls transmit shutdown for the inactive bus. when the bsdtxo bit in the master confguration register equals 0, the inactive bus receiver is also shutdown (full bus shutdown vs. only transmit shutdown). the device affrms shutdown status by setting the corresponding shutdown status bits 15-12 in the applicable rt bit register(s), address 0x001e for rt1, or 0x0027 for rt2. with autobsd bit set, upon receiving mc5 (or mc21 with data word matching bus select criteria), the device automatically re-enables both transmit and receive for the inactive bus (without regard to bsdtxo bit in the master confguration register). the device affrms shutdown override status by resetting corresponding shutdown status bits 15-12 in the applicable rt bit register(s), address 0x001e for rt1, 0x0027 for rt2. HI-6130, hi-6131
holt integrated circuits 148 bit no. mnemonic r/w reset function 3 ? 2 mc17op1:0 r/w 0 mc17 sync option bits 1:0 if register bits 3-2 equal 11, the data word received with a valid synchronize mode command (mc17) is unconditionally loaded into the time-tag counter, at address 0x0047 for rt1 or 0x0049 for rt2. for non-broadcast mc17 commands, the counter load occurs before status word transmission. if register bits 3-2 equal 00, the external host assumes responsibility for actions needed to perform synchronize duties upon reception of the valid mc17 synchronize mode code command, but status transmission automatically occurs. the binary 01 and 10 combinations of register bits 3-2 support certain extended subaddress schemes. if bits 3-2 equal 01, the received data word is automatically loaded into the time-tag counter if bit 0 of the received data word equals 0. the counter resides at address 0x0047 for rt1 or 0x0049 for rt2. if bits 3-2 equal 10, the received data word is automatically loaded into the time-tag counter if bit 0 of the received data word equals 1. for non-broadcast mc17 commands, the counter load occurs before status word transmission. 1 mc16opt r/w 0 host reset of service request status bit for mode code 16. if this bit is logic 0, reception of a transmit vector word mode command (mc16) causes automatic reset of the service request status bit. the service request bit is reset in the status word bits register before status word transmission begins. if the mcopt1 bit is logic 1, the external host assumes responsibility for resetting the service request bit in the status word bits register. 0 mc8opt r/w 0 automatic soft reset for mode code 8. if this bit is logic 0, reception of a reset remote terminal mode command (mc8) causes automatic assertion of sreset software reset. if non-broadcast mode command, reset occurs after status word transmission is complete. if this bit is logic 1, the external host assumes responsibility for actions needed to perform terminal reset. 18.2. remote terminal 1 (rt1) operational status register (0x0018) remote terminal 2 (rt2) operational status register (0x0021) rta2 rtap rta4 lock reserved reserved reserved mctd rtapf rta1 0 rta0 bit 15 14 13 12 11 10 0 0 0 0 0 these bits latch pins 0 0 reserved mcnd mcrd r rta3 reserved rw (see lock bit 9) mr reset host access bit 9 8 7 6 5 4 3 2 1 0 0 at rising edge on the mr master reset input pin, register bits 15-9 capture the logic states (0 or 1) of the correspond - ing input pins having like names. after reset, register bits 15-9 can be overwritten only if lock bit 9 is logic 0. if the register lock bit is logic 1, these bits are read-only. bits 8-0 are read-only; these bits are cleared after mr pin master reset, but are unaffected by assertion of rtxreset HI-6130, hi-6131
holt integrated circuits 149 remote terminal software reset in the master status and reset register (0x0001). bit no. mnemonic r/w reset function 15 ? 11 10 rta4:0 rtap r/w 0 remote terminal address bits 4-0. remote terminal address parity. these bits refect the active remote terminal address. they refect the state of the input pins rta4 through rta0 that applied at the rising edge of the mr master reset input signal. the rtap bit, when appended to the remote terminal address bits, provides odd parity. if the register lock bit is high, bits 15-10 are read-only. if the register lock bit is low, the host can overwrite these bits change the terminal address and parity. 9 lock r/w 0 remote terminal address lock. this bit refects the state of the lock input pin that applied at the rising edge of the mr master reset input signal. after reset, the host can overwrite bits 15-9 only if register lock bit 9 is logic 0. when the lock bit is high, the host cannot overwrite register bits 15-9. to restore host write capability for these bits, the mr master reset input signal must frst be asserted with the lock input pin held low to restore register lock bit 9 to logic 0. 8 ? 6 reserved r 0 these bits are not used. 5 4 3 mcnd mcrd mctd r 0 no data mode command flag. receive data mode command flag. transmit data mode command flag. these three bits refect the type of command stored in the rt current command register: current command type bits 5-4-3 current command word subaddress, not mode code mode code, no data word mode code, received word mode code, transmit word mode code, undefned 000 100 010 001 111 subaddress, transmit or receive mc0 to mc15, t/ r bit = 1 mc16 to mc31, t/ r bit = 0 mc16 to mc31, t/ r bit = 1 mc0 to mc15, t/ r bit = 0 2 rtapf r 0 remote terminal address parity fail. this bit is set when rt address parity error occurs for the value contained in register bits 15-10. it is low when correct odd parity applies for bits 15-10. 1 ? 0 reserved r 0 these bits are not used. HI-6130, hi-6131
holt integrated circuits 150 18.3. remote terminal 1 (rt1) current command register (0x0002) remote terminal 2 (rt2) current command register (0x0004) r mr reset host access bit 15 14 13 12 11 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 8 7 6 5 4 3 2 1 0 register value msb lsb these 16-bit registers are read-only and are fully maintained by the device. these registers are cleared after mr pin master reset, but are unaffected by assertion of rtxreset remote terminal software reset in the master status and reset register (0x0001). this register contains the last valid command word received by the remote terminal over either mil-std-1553 bus. this register is updated 5s after the active output is asserted. 18.4. remote terminal 1 (rt1) current control word address register (0x0003) remote terminal 2 (rt2) current control word address register (0x0005) r mr reset host access bit 15 14 13 12 11 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 8 7 6 5 4 3 2 1 0 register value msb lsb these 16-bit registers are read-only and are fully maintained by the device. these registers are cleared after mr pin master reset, but are unaffected by assertion of rtxreset remote terminal software reset in the master status and reset register (0x0001). these registers contain the address for the descriptor table control word corresponding to the current command stored in the current command register, above. these registers are updated 5 s after the active output is as - serted for recognition of a valid command for the rt. also see description for the current message information word address register. 18.5. remote terminal 1 (rt1) descriptor table base address register (0x0019) remote terminal 2 (rt2) descriptor table base address register (0x0022) register address 0x0019 (rt1) msb 0 0 1 0 0 0 0 0 0 0 0 0 0 0 lsb rw 0 0 register value r r mr reset host access bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 register address 0x0019 (rt1) msb 0 0 0 1 0 0 0 0 0 0 0 0 0 0 lsb rw 0 0 register value r r mr reset host access bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 these 16-bit registers are read-write and contain the starting address for the remote terminals descriptor table. HI-6130, hi-6131
holt integrated circuits 151 these registers are initialized with default values after mr pin master reset, or by assertion of rtxreset remote terminal software reset in the master status and reset register (0x0001). for rt1, the post-reset register value is 0x0200. for rt2, the post-reset register value is 0x0400. after initialization, these registers are fully maintained by the host. bit 15 and bits 8:0 cannot be set and will always read logic 0. 18.6. remote terminal 1 (rt1) mil-std-1553 status word bits register (0x001a) remote terminal 2 (rt2) mil-std-1553 status word bits register (0x0023) me txandclr inst svcreq busy ssysf 0 bit 0 0 0 0 0 0 0 0 0 0 0 tf bcr r reserved 0 0 reserved rw reserved reserved reserved reserved reserved reserved rw 0 0 r rw rw mr reset host access 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 these 16-bit registers are read-write. with the exception of bits 4 and 10, these registers are maintained by the host. these registers are cleared after mr pin master reset, or by assertion of rtxreset remote terminal software reset in the master status and reset register (0x0001). register bits 14-10 and 7-4 are read-only. most of these bits read back zero, except for bits 4 and 10, which are main - tained by the device. the remaining bits in the register are read-write and are maintained by the host. all bits are active high. register bits 10-0 are refected in the outgoing mil-std-1553 rt status word. the rt status word refects the state of host-written register bits until overwritten by the host, unless the transmit and clear function (bit 15) is enabled. when set, the transmit and clear bit resets itself and bits 9-5 and 3-0 after the next transmitted status word. bit no. mnemonic r/w reset function 15 txandclr r/w 0 transmit and clear. when this bit is set, it resets itself and bits 9-5 and 3-0 after the next transmitted status word. this bit does not affect operation of the transmit status word and transmit last command mode codes. example: transaction of a valid legal command with the inst and txandclr bits asserted results in status word transmission with the instrumentation bit set. if the following command is transmit status or transmit last command mode code, the instrumentation bit remains set. 14 ? 11 reserved r 0 these bits are not used, cannot be written, always read back 000. 10 me r 0 message error status bit. the device maintains this read-only bit, based on prior message results. 9 inst r/w 0 instrumentation status bit. the host maintains this read-write bit. 8 svcreq r/w 0 service request status bit. the host maintains this read-write bit. 7 ? 5 reserved r 0 these bits are not used, cannot be written, always read back 000. HI-6130, hi-6131
holt integrated circuits 152 bit no. mnemonic r/w reset function 4 bcr r 0 broadcast command received status bit. the device maintains this read-only bit, based on prior message results. 3 busy r/w 0 busy status bit. the host maintains this read-write bit. when set, the rt asserts its busy bit in status response for all valid commands. instead of enabling busy for all commands, the host can assert busy status for selected commands by asserting the busy bit in descriptor table control words for the individual commands. when response to a command conveys busy status, the rt suppresses transmission of data words that would normally accompany status for transmit commands. for messages transacted with busy status, the wasbusy fag is asserted in the stored message information word. 2 ssysf r/w 0 subsystem fail status bit. the host maintains this read-write bit. this register bit is logically ored with the rts ssysf input pin. if either ssysf register bit or ssysf pin is asserted, the ssysf subsystem flag status bit is set. if the rts confguration register mcopt1 bit equals 0, reception of a transmit vector word mode command (mc16) causes automatic reset of the ssysf status bit in this register; when this occurs, the register bit is reset before status word transmission begins. 1 dbc r 0 dynamic bus control status bit. the host maintains this read-write bit. 0 tf r/w 0 terminal flag status bit. the host maintains this read-write bit. when this bit is asserted, the terminal flag status bit is set. if the terminal flag bit is set while responding to subaddress transmit commands or mode code commands 16-31 that normally transmit a data word, all data word transmission is suppressed. 18.7. remote terminal 1 (rt1) current message information word register (0x001b) remote terminal 2 (rt2) current message information word register (0x0024) r mr reset host access bit 15 14 13 12 11 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 8 7 6 5 4 3 2 1 0 register value msb lsb these 16-bit registers are read-only and are fully maintained by the device. these registers are cleared after mr pin master reset, but are unaffected by assertion of rtxreset remote terminal software reset in the master status and reset register (0x0001). this register contains the data buffer address (assigned in the terminals descriptor table) corresponding to the last decoded valid command for the remote terminal. this register is updated 5s after the active output is asserted. the value in this register points to the commands message information word (or miw) in the descriptor table, the HI-6130, hi-6131
holt integrated circuits 153 value of the current command word itself is stored in the current command register for the remote terminal, rt1 or rt2. 18.8. remote terminal 1 (rt1) bus a select register (0x001c) remote terminal 2 (rt2) bus a select register (0x0025) rw mr reset host access bit 15 14 13 12 11 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 8 7 6 5 4 3 2 1 0 register value msb lsb these 16-bit registers are read-write and are fully maintained by the host. these registers are cleared after mr pin master reset, but are unaffected by assertion of rtxreset remote terminal software reset in the master status and reset register (0x0001). the bus a select register is only used when the autobsd bit in the rt confguration register equals 1. this autobsd setting means the device automatically fulflls mode commands mc20 (decimal) selected transmitter shutdown or mc21 override selected transmitter shutdown. transmitter shutdown or shutdown override can only occur for the inactive bus. if either mode command is received on bus b, the inactive bus is bus a. the device compares the received mode data word to the contents of the bus a select register to determine whether inactive bus a is selected for transmitter shutdown or transmitter shutdown override. (bus shutdown or shutdown override can only occur for the inactive bus.) if the data word matches the value stored in the bus a select register and autobsd equals 1, the device automatically fulflls mc20 transmitter shutdown or mc21 shutdown override without host assistance: if the mode command received was mc20 (bus shutdown), the transmit shutdown a bit in the rts bit (built-in test) word register is asserted. if mode command mc21 (override bus shutdown) was received, the transmit shutdown a bit in the bit word register is negated. 18.9. remote terminal 1 (rt1) bus b select register (0x001d) remote terminal 2 (rt2) bus b select register (0x0026) rw mr reset host access bit 15 14 13 12 11 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 8 7 6 5 4 3 2 1 0 register value msb lsb these 16-bit registers are read-write and are fully maintained by the host. these registers are cleared after mr pin master reset, but are unaffected by assertion of rtxreset remote terminal software reset in the master status and reset register (0x0001). the bus b select register is only used when the autobsd bit in the rt confguration register equals 1. this auto - bsd setting means the device automatically fulflls mode commands mc20 (decimal) selected transmitter shutdown or mc21 override selected transmitter shutdown. transmitter shutdown or shutdown override can only occur for the inactive bus. if either mode command is received on bus a, the inactive bus is bus b. the device compares the received mode data word to the contents of the bus b select register to determine whether inactive bus b is selected for transmitter shutdown or transmitter shutdown override. (bus shutdown or shutdown override can only occur for the inactive bus.) if the data word matches the value stored in the bus b select register and autobsd equals 1, the device automatically fulflls mc20 transmitter shutdown or mc21 shutdown override without host assistance: if the mode command received was mc20 (bus shutdown), the transmit shutdown b bit in the rts bit (built-in test) word register is asserted. if mode command mc21 (override bus shutdown) was received, the transmit shutdown b bit in the bit word register is negated. HI-6130, hi-6131
holt integrated circuits 154 18.10. remote terminal 1 (rt1) built-in test (bit) word register (0x001e) remote terminal 2 (rt2) built-in test (bit) word register (0x0027) rxasd txasd user assigned bits rt rxbsd 0 0 0 0 0 0 0 0 p p 0 0 tfbinh rw txbsd 0 0 eelf 0 r lbfa lbfb bmtf 0 r mr reset host access bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bits 11-6 in these 16-bit registers are read-write; the remaining bits are read-only. the ten assigned bits are written by the device when predetermined events occur. the host may overwrite the device-written bits 5 and 4. after mr pin master reset, bits 13-12, 5-4 and 0 are reset. bits 15-14 will be set if the corresponding txinha or txinhb input pins are high. bits 3-1 will be set if rt address parity error, or post-mr memory test failure or auto-initialization failure occurred. these registers are not affected by assertion of rtxreset remote terminal software reset in the master status and reset register (0x0001). remote terminals rt1 and rt2 use independent bit word registers. if the altbitw option bit in the rt1 or rt2 confguration register is zero when a valid transmit bit word mode command (mc19) is received, the current value in this register is transmitted as the mode data word in the terminal response. the value is also copied to the remote terminals assigned data buffer for mc19, after mode command fulfllment. bit no. mnemonic r/w reset function 15 14 txasd txbsd r 0 transmit bus a shutdown. transmit bus b shutdown. these read-only bits are set when the corresponding bus transmitter was disabled by assertion of the bus txinha or txinhb input pin, or by fulfllment of a transmitter shutdown mode command, either mc4 or mc20. refer to the description for the bsdtxo bit in the master confguration register ( page 29 ) and the description for the autobsd bit in the rt confguration register for further information. 13 12 rxasd rxbsd r 0 receive bus a shutdown. receive bus b shutdown. these read-only bits are set when the corresponding bus receiver was disabled concurrently with a bus transmitter by a transmitter shutdown mode command mc4 or mc20. refer to the description for the bsdtxo bit in the master confguration register (section 9.1 ) and the description for the autobsd bit in the rt confguration register for further information. 11 ? 6 ---------- r/w 0 user assigned bits. 5 4 lbfa lbfb r 0 bus a loopback fail. bus b loopback fail. these read-only bits are set if bus a or bus b loopback failure occurs during self-test (see section 24.2.1. self-test control register (0x0028) on page 226 ). HI-6130, hi-6131
holt integrated circuits 155 bit no. mnemonic r/w reset function 3 bmtf r 0 bist memory test fail. this bit is set if error occurs during built-in self-test for device random access memory (ram) (see section 24.2.1. self-test control register (0x0028) on page 226 ). 2 rtapf r 0 rt address parity fail. this bit is asserted when an rt1 or rt2 operational status register bits 15:10 refect parity error. after mr master reset, bits 15:10 in the rts operational status register refect input pin states, but will be overwritten if subsequent auto-initialization is performed (if autoen pin is high) and the initialization eeprom contains different data for rt operational status register bits 15:10. 1 eelf r 0 auto-initialization eeprom load fail. this bit only applies when auto-initialization is enabled (autoen input pin state equals 1). this bit is set if, after mr master reset, failure occurs when copying serial eeprom to registers and ram. when this occurs, bit 0 or bit 1 will be set in the rts operational status register (0x0002) to indicate type of failure. 0 tfbinh r 0 this bit is set when the terminal flag status bit is disabled while fulflling an inhibit terminal fag bit mode code command (mc6). this bit is reset if terminal fag status bit disablement is cancelled later by an override inhibit terminal fag bit mode code command (mc7). 18.11. remote terminal 1 (rt1) alternate built-in test (bit) word register (0x001f) remote terminal 2 (rt2) alternate built-in test (bit) word register (0x0028) rw mr reset host access bit 15 14 13 12 11 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 8 7 6 5 4 3 2 1 0 register value msb lsb this 16-bit register is read-write and is fully maintained by the host. this register is cleared after mr pin master reset. it is not affected by assertion of rtxreset remote terminal software reset in the master status and reset register (0x0001). if the altbitw option bit in the rt1 or rt2 confguration register equals one when a valid transmit bit word mode command (mc19) is received, the current value in this register is transmitted as the mode data word in the terminal response. the value is also copied to the assigned data buffer for mc19, after mode command fulfllment. 18.12. remote terminal 1 (rt1) time tag counter register (0x0049) remote terminal 2 (rt2) time tag counter register (0x004b) r mr reset host access bit 15 14 13 12 11 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 8 7 6 5 4 3 2 1 0 register value msb lsb HI-6130, hi-6131
holt integrated circuits 156 this register is read-only and is cleared after mr pin master reset or assertion of rtxreset remote terminal software reset in the master status and reset register (0x0001). reads to this register address return the current value of the free running 16-bit time tag counter. counter resolution is programmed by the ttck2:0 bits in the time tag confguration register. options are: 2, 4, 8, 16, 32 and 64s, or externally provided clock. the same clock source is shared by rt1, rt2 and the bc. the device automatically resets the time-tag counter when a synchronize mode command without data (mc1) is received. in addition, the host can reset, load or capture the time tag count at any time by asserting action bits in the time tag confguration register. load and capture operations utilize the rt time tag utility registers, described below. the mc17op1:0 bits in the remote terminal confguration registers allow automatic loading of time-tag count using the data word received with a synchronize with data mode command, mc17. if both of these bits equal one, the data word received with a valid synchronize mode command (mc17) is unconditionally loaded into the time-tag counter. for non-broadcast mc17 commands, the counter load occurs before status word transmission. if both mc17op1 and mc17op0 bits equal 0, the external host assumes responsibility for actions needed to perform synchronize duties upon reception of the valid mc17 synchronize command, but status transmission occurs automatically. the binary 01 and 10 combinations of these bits support certain extended subaddressing schemes. if the mc17op1:0 bits equal 01, the received data word is automatically loaded into the time-tag counter if the low order bit of the re - ceived data word (bit 0) equals 0. if the mc17op1:0 bits equal 10, the received data word is automatically loaded into the time-tag counter if the low order bit of the received data word (bit 0) equals 1. for non-broadcast mc17 com - mands, the counter is loaded before status word transmission. 18.13. remote terminal 1 (rt1) time tag utility register (0x004a) remote terminal 2 (rt2) time tag utility register (0x004c) rw mr reset host access bit 15 14 13 12 11 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 8 7 6 5 4 3 2 1 0 register value msb lsb these 16-bit registers are read-write and are fully maintained by the host. these registers are cleared after mr pin master reset, but are not affected by assertion of rtxreset remote terminal software reset in the master status and reset register (0x0001). these registers have two functions associated with the two free-running remote terminal time tag counters: 18.13.1. rt time tag counter loading when the rt1tta1-0 bits 9-8 in time tag counter confguration register 0x0039 are written to 1-0, the value con - tained in the rt1 time tag utility register (0x0048) is loaded into the rt1 time tag counter (0x0047). when the rt2tta1-0 bits 11-10 in time tag counter confguration register 0x0039 are written to 1-0, the value contained in the rt2 time tag utility register (0x0049) is loaded into the rt2 time tag counter (0x004a). 18.13.2. rt time tag count match interrupts if the rt1ttm or rt2ttm interrupts are enabled in the hardware interrupt enable register (0x000f), then time tag count match interrupts are enabled. when enabled for rt1, the hardware rt1ttm interrupt occurs when the free running rt1 time tag counter (0x0047) matches the value contained in the rt1 time tag utility register (0x0048). when enabled for rt2, the hardware rt2ttm interrupt occurs when the free running rt2 time tag counter (0x0049) matches the value contained in the rt2 time tag utility register (0x004a). HI-6130, hi-6131
holt integrated circuits 157 18.14. rt1 and rt2 remote terminal interrupt registers and their use section 9.4 on page 36 through section 9.6 describe how the host uses three hardware interrupt registers, the interrupt log buffer and the interrupt count & log address register to manage interrupts. when rt1/rt2 is enabled, three additional registers are dedicated to the rt1/rt2 interrupts. comparable to the hardware interrupt register triplet, rt1/rt2 has ? a rt1/rt2 interrupt enable register to enable and disable interrupts ? a rt1/rt2 pending interrupt register to capture the occurrence of enabled interrupts ? a rt1/rt2 interrupt output enable register to enable irq output to host, for pending enabled interrupts each individual bit in all three registers is mapped to the same interrupt-causing event when the corresponding interrupt condition is enabled. numerous interrupt options are available for rt1/rt2. at initialization, bits are set in the rt1/rt2 interrupt enable register to identify the interrupt-causing events for rt1/rt2 which are heeded by the hi-613x. most rt1/rt2 applications only use a subset of available rt1/rt2 interrupt options. interrupt-causing events are ignored when their corresponding bits are reset in the rt1/rt2 interrupt enable register. setting an interrupt enable register bit from 0 to 1 does not trigger interrupt recognition for events that occurred while the bit was zero. whenever a rt1/rt2 interrupt event occurs (and the corresponding bit is already set in the rt1/rt2 interrupt enable register), these actions occur: ? the interrupt log buffer is updated. ? a bit corresponding to the interrupt type is set in the rt1/rt2 pending interrupt register. the type bit is logically- ored with the preexisting register value, retaining bits for prior, unserviced rt1/rt2 interrupts. ? rt interrupt pending (rtip) bit 1 shared by rt1 and rt2 is set in the hardware pending interrupt register. the rtip bit is logically-ored with the preexisting register value, retaining bits for unserviced hardware interrupts and the preexisting status of the bcip and mtip (bus controller and mt) interrupt pending bits. ? if the matching bit is already set in the rt1/rt2 interrupt output enable register, an irq output occurs. if the matching bit in the rt1/rt2 interrupt output enable register was not already set (i.e., low priority polled interrupt), the host can poll the rt1/rt2 pending interrupt register to detect the occurrence of rt1/rt2 interrupts, indicated by non-zero value. reading the rt1/rt2 pending interrupt register automatically clears it to 0x0000. a single irq host interrupt output signal is shared by all enabled interrupt conditions having bits set in the four interrupt output enable registers (hardware, bc, rt and smt or imt). multiple interrupt-causing events can occur simultaneously, so single or simultaneous interrupt events can assert the irq host interrupt output. when the host receives an irq signal from the device, it identifes the event(s) that triggered the interrupt. section 9.4 describes two methods for identifying the interrupt source(s). one scheme uses the three low order bits in the hardware pending interrupt register to indicate when bc, rt, smt and/or imt interrupts occur. when rt interrupt pending (rtip) bit 1 shared by rt1 and rt2 is set in the hardware pending interrupt register, the rt1/rt2 pending interrupt register contains a nonzero value and may be read next to identify the specifc rt1/rt2 interrupt event(s). or, the host can directly interrogate the interrupt count & log address register, followed by the interrupt log buffer. data sheet section 9.4 has a detailed description. HI-6130, hi-6131
holt integrated circuits 158 18.14.1. remote terminal (rt) interrupt enable register (0x0012) ilcmd2 iwa2 rt2mc8 reserved ixeqz1 ibr1 ilcmd1 iwa1 reserved ibr2 0 merr2 0 0 0 0 0 0 0 0 0 0 0 0 reserved merr1 rw ixeqz2 0 reserved rt1mc8 0 0 r mr reset host access bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 18.14.2. remote terminal (rt) pending interrupt register (0x0009) ilcmd2 iwa2 rt2mc8 reserved ixeqz1 ibr1 ilcmd1 iwa1 reserved ibr2 0 merr2 0 0 0 0 0 0 0 0 0 0 0 0 reserved merr1 ixeqz2 0 reserved rt1mc8 0 0 r mr reset host access bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 18.14.3. remote terminal (rt) interrupt output enable register (0x0016) ilcmd2 iwa2 rt2mc8 reserved ixeqz1 ibr1 ilcmd1 iwa1 reserved ibr2 0 merr2 0 0 0 0 0 0 0 0 0 0 0 0 reserved merr1 rw ixeqz2 0 reserved rt1mc8 0 0 r mr reset host access bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 three registers govern rt interrupt behavior: the rt interrupt enable register, the rt pending interrupt register and the rt interrupt output enable register. when a bit is set in the rt pending interrupt enable register, the corresponding rt interrupt is enabled. when a bit is reset in this register, the corresponding interrupt event is unconditionally disregarded. setting a register bit from 0 to 1 does not trigger interrupt recognition for events that occurred while the bit was zero. when an enabled rt interrupt event occurs, the corresponding bit is set in the pending rt interrupt register and the interrupt log buffer is updated. to simplify interrupt decoding, rtip bit 2 in the hardware pending interrupt register is also set whenever a message sets at least one bit in the rt pending interrupt register. if the corresponding bit is set in the rt interrupt output enable register, the irq output is asserted at message completion. the rt interrupt output enable register establishes two priority levels: high priority interrupts generate an irq output while low priority interrupts do not. both priority levels update the pending interrupt register and interrupt log buffer. the host can detect low priority (masked) interrupts by polling pending interrupt registers. the following table describes the shared bit descriptions used by all three rt interrupt registers. HI-6130, hi-6131
holt integrated circuits 159 bit no. mnemonic function 15 rt2mc8 rt2 mode code 8 command interrupt. remote terminal rt2 processed a valid mil-std-1553 reset remote terminal mode code command. an rtxmc8 interrupt notifes the host when the bus controller commands remote terminal reset. the state of bit 0 in the rt2 remote terminal confguration register 0x0020 determines whether the mode code response is automatic or handled by the host. if the rt2mc8 bit is reset in the rt interrupt enable register when rt2 decodes a valid reset remote terminal mode command, bit 0 in the rt2 remote terminal confguration register dictates whether the reset response is automatic, or host controlled. the event does not affect the rt pending interrupt register, the interrupt log or the irq output, but the rt2mc8 output pin is asserted to indicate that rt2 needs reset. in the case of a broadcast command to rt31, both mc8 pins will be asserted. 14 ixeqz2 rt2 index equals zero interrupt. the index equals zero (ixeqz) interrupt for rt2. index counts are used in multi- message bulk data transfers. index equals zero occurs when the last expected message was transacted. defned ixeqz interrupt events comprise: (a) subaddresses using indexed buf fer mode when the index decrements from 1 to 0, or (b) subaddresses using circular buffer modes when the pre-determined number of messages has been transacted. 13 ilcmd2 rt2 illegal command interrupt. the remote terminal 2 encountered a valid illegal message, as defned in the rt2 illegal command table. illegal commands are detected when a new valid command word is decoded and the rt2 illegalization table bit corresponding to the received command is logic 1. (table bits are logic 0 for legal commands.) the rt2 illegalization table contains nonzero values only when illegal command detection is being applied. when illegal commands are received, rt2 responds by transmitting a status word with me message error fag set; no data words are transmitted. if the ilcmd2 bit is reset in the rt interrupt enable register when a valid illegal command is decoded, the event does not affect the rt pending interrupt register, the interrupt log or the irq output. 12 ibr2 rt2 broadcast command received interrupt. broadcast commands are enabled for remote terminal 2 and the terminal encountered a valid command addressed to rt31, the broadcast command address. 11 merr2 rt2 message error status interrupt. the remote terminal 2 set its message error status fag while processing a valid mil- std-1553 message. message errors are caused by manchester encoding problems or protocol errors. 10 iwa2 rt2 interrupt when accessed. the remote terminal 2 processed a valid mil-std-1553 command having the iwa interrupt enabled in its rt2 descriptor table entry. iwa interrupts are used to notify the host each time certain command words are encountered. 9 reserved bit 9 cannot be written and reads back logic 0. HI-6130, hi-6131
holt integrated circuits 160 bit no. mnemonic function 8 rt1mc8 rt1 mode code 8 command interrupt. remote terminal rt1 processed a valid mil-std-1553 reset remote terminal mode code command. an rtxmc8 interrupt notifes the host when the bus controller commands remote terminal reset. the state of bit 0 in the rt1 remote terminal confguration register 0x0017 determines whether the mode code response is automatic or handled by the host. if the rt1mc8 bit is reset in the rt interrupt enable register when rt1 decodes a valid reset remote terminal mode command, bit 0 in the rt1 remote terminal confguration register dictates whether the reset response is automatic, or host controlled. the event does not affect the rt pending interrupt register, the interrupt log or the irq output, but the rt1mc8 output pin is asserted to indicate that rt1 needs reset. in the case of a broadcast command to rt31, both mc8 pins will be asserted. 7 ixeqz1 rt1 index equals zero interrupt. the index equals zero (ixeqz) interrupt for rt1. index counts are used in multi- message bulk data transfers. index equals zero occurs when the last expected message was transacted. defned ixeqz interrupt events comprise: (a) subaddresses using indexed buf fer mode when the index decrements from 1 to 0, or (b) subaddresses using circular buffer modes when the pre-determined number of messages has been transacted. 6 ilcmd1 rt1 illegal command interrupt. the remote terminal 1 encountered a valid illegal message, as defned in the rt1 illegal command table. illegal commands are detected when a new valid command word is decoded and the rt1 illegalization table bit corresponding to the received command is logic 1. (table bits are logic 0 for legal commands.) the rt1 illegalization table contains nonzero values only when illegal command detection is being applied. when illegal commands are received, rt1 responds by transmitting a status word with me message error fag set; no data words are transmitted. if the ilcmd1 bit is reset in the rt interrupt enable register when a valid illegal command is decoded, the event does not affect the rt pending interrupt register, the interrupt log or the irq output. 5 ibr1 rt1 broadcast command received interrupt. broadcast commands are enabled for remote terminal 1 and the terminal encountered a valid command addressed to rt31, the broadcast command address. 4 merr1 rt1 message error status interrupt. the remote terminal 1 set its message error status fag while processing a valid mil- std-1553 message. message errors are caused by manchester encoding problems or protocol errors. 3 iwa1 rt1 interrupt when accessed. the remote terminal 1 processed a valid mil-std-1553 command having the iwa interrupt enabled in its rt1 descriptor table entry. iwa interrupts are used to notify the host each time certain command words are encountered. 2 ? 0 reserved bits 2-0 cannot be written, and read back 000. HI-6130, hi-6131
holt integrated circuits 161 19. remote terminal rt1 and rt2 configuration and operation 19.1. command responses a brief review of mil-std-1553 commands and responses is appropriate here to establish terminology used in the rest of this data sheet. shown in figure 12 , each command word is comprised of a sync feld, three 5-bit data felds, a single bit denoting transmit / receive direction and ends with a parity bit. the hardware decoder uses the sync feld to determine word type (command vs. data). word validity is based on proper sync encoding, manchester ii encoding, correct bit count and correct odd parity for the 16 data bits. once a valid word with command sync is found, the sync and parity are stripped before the commands 16 data bits are stored for further processing. command sync terminal address field subaddress (sa) field word count field * t/ r bi t parity bit * word count field is replaced by mode code field when the sa field equals 0x00 or 0x1f figure 12. mil-std-1553 command word structure a valid command can be specifcally addressed to the individual HI-6130 terminal (the command words embedded terminal address feld matches the terminal address latched in the operational status register) or can be a broad - cast command addressed to all terminals. broadcast commands are always addressed to rt address 31 (0x1f). in systems where broadcast commands are disallowed, rt31 is not used as a conventional terminal address. when set, the bcstinv bit in the rt confguration register renders rt31 commands as invalid: broadcast commands are indistinguishable from commands addressed to other terminals. invalid commands are simply disregarded. when the command words 5-bit sa (subaddress) feld is in the range of 1 to 30 (0x01 to 0x1e) the command is con - sidered a subaddress command. the terminal will either receive or transmit data words, and direction is specifed by the commands t/ r bit. the number of data words transacted is specifed in the 5-bit word count feld, ranging from 1 to 32 words. thirty-two data words is represented when the word count feld equals 0x00. when the commands 5-bit subaddress feld equals 0 or 31 (0x1f) a mode code command is indicated; the low order fve bits no longer specify a word count, instead they convey a mode code value. this data sheet refers to mode code commands by the mode code number. for example, a mode command with 5-bit mode code feld of 0x10 is called mc16, and the full range of mode code values is mc0 through mc31 (decimal). mode codes mc16 through mc31 (0x10 through 0x1f) have a single associated data word. when the command t/ r bit equals 0, the data word is contiguous with the command word and received by the rt. when the commands t/ r bit equals 1, the data word is transmitted by the rt, following the terminals transmitted status word. mode codes mc0 through mc15 (0x0f) do not have associated data words. for these 16 commands, the command t/ r bit does not specify direction. these commands must be transmitted with t/ r bit equal to 1. if the t/ r bit is 0, the mode command is undefned. twenty-two mode commands are undefned mode commands in mil-std-1553b: mode codes 0 through 15 with t/r bit = 0 mode codes16, 18 and19 with t/r bit = 0 mode codes 17, 20 and 21 with t/r bit = 1 the umcinv bit in the rt confguration register determines how these undefned mode commands are handled by HI-6130, hi-6131
holt integrated circuits 162 the HI-6130/31. if the umcinv confguration bit equals 1, the undefned mode commands are treated as invalid. they are not recognized by the device. there is no terminal response and status is not updated. if the umcinv confguration bit equals 0, the 22 undefned mode commands are considered valid; this is the default condition following reset. for this case, terminal response depends on whether or not the application uses illegal command detection. if illegal command detection is not used , all illegalization table entries should be logic 0, including the 22 entries for these undefned commands. (the illegalization table is fully described in section 19.2 on page 163 . after mr reset, all entries equal logic 0.) the terminal responds in form, transmitting clear status (and a single mode data word if the command is mc17, mc20 or mc21 with t/ r bit = 1). terminal status is updated. if illegal command detection applies, the illegalization table entries for these 22 undefned commands should be initialized to logic 1. in this case, the terminal will respond with status word only, with message error bit set. no mode data word is transmitted. terminal status is updated. twenty-seven mode codes are considered reserved in mil-std-1553b: mode codes 9 through 15 with t/r bit = 1 mode codes 22 through 31 with t/r bit = 1 mode codes 22 through 31 with t/r bit = 0 treatment of these reserved mode commands depends on their respective illegalization table entries. as described above for undefned mode commands, response depends on whether or not illegal command detection applies. any mode commands not implemented in the HI-6130/31 terminal should be treated the same as reserved mode com - mands. for example, command mc0 (with t/ r = 1) is probably unimplemented because the HI-6130 does not have provisions for accepting dynamic bus control. the important point is that illegal command detection should be universally applied (or not applied) when setting up a HI-6130/31 remote terminal application. here are the two options: not using illegal command detection. the HI-6130/31 illegalization table is left in its default state (all locations equal to mr post-reset 0x0000). the terminal responds in form to all valid commands, whether legal or illegal. using illegal command detection. the HI-6130/31 illegalization table is initialized by the host to implement illegal command detection. the host sets bits for all illegal commands. this generally includes the reserved and unimple - mented mode commands, unimplemented subaddresses (or specifc word counts, t/ r bit states, and/or broadcast vs. non-broadcast status within subaddresses). treatment for the undefned mode commands depends on umcinv bit. the host defnes terminal response for all individual commands by initializing the descriptor table, fully described later. at this point, a few comments about the descriptor table are appropriate. the command sa (subaddress) feld has a range of 0 to 31 (0x1f). when sa is in the range 1 to 30 (0x1e), the com - mand is a transmit or receive subaddress command. the number of data words transmitted or received is expressed in the low order 5 bits. when sa equals 0 or 31 (0x1f) the command is a mode command and the mode code value is expressed in the low order 5 bits. for each subaddress, separate table descriptor blocks for transmit and receive commands permit different data buff - ering to be applied. the host initializes the table so each transmit-subaddress and each receive-subaddress uses one of four methods for storing message data. during table initialization, memory is allocated in shared ram for storing message data according to the application requirements. each transmit-subaddress and receive-subaddress has one or more data pointers (depending on buffer method) addressing its reserved data buffer(s). each mode command also has its own table descriptor block. mode commands have either one data word or no as - sociated data words. descriptor words used as data pointers by subaddress commands are instead used for direct storage of transacted mode data words. mode commands that transmit or receive mode data words have a dedicated storage address range in shared ram, eliminating the need for descriptor table data pointers. each mode command with mode data word has its own fxed address for data storage. this includes reserved mode HI-6130, hi-6131
holt integrated circuits 163 codes with data word. thus the HI-6130/31 can respond consistently for all mode commands; transmitted data values for in form responses (when illegal command detection is not used) can be predetermined, even for the reserved mode commands. 19.1.1. rt to rt commands. the mil-std-1553 standard allows for data word transmission from a specifed transmitting terminal to a different receiving terminal. when broadcast commands are allowed, data transmission can be addressed to the broadcast terminal address, rt31. if broadcast is allowed, the host should initialize the bcstinv (broadcast invalid) bit in the rt confguration register to logic 0. all rt to rt commands are characterized by a pair of contiguous command words: command word 1 is a receive command addressed to the intended receiving terminal, then command word 2 is a transmit command addressed to a single transmitting terminal. command word 2 cannot be broadcast address rt31. the HI-6130 automatically de - tects and handles rt to rt commands, except when either command word contains a subaddress feld equal to 0x0 or 0x1f. either subaddress value indicates a mode code command; the device treats rt to rt commands with mode code as invalid. if either rt-rt command word is addressed to the HI-6130/31 terminal but contains subaddress 0x0 or 0x1f, the command is not recognized; there is no rt command response, and no status updating for the beneft of following transmit status or transmit last command mode commands. when either rt-rt command word (with subaddress feld not equal to 0x0 or 0x1f) is addressed to the HI-6130/21 terminal, but the other command word contains subaddress 0x0 or 0x1f, the rt-rt command is not recognized as valid. there is no rt command response, and no status updating for the beneft of following transmit status or trans - mit last command mode commands. an rt-rt command pair where command word 1 is addressed to the HI-6130/21 terminal and command word 2 is addressed to a different terminal is considered an rt-rt receive command. when the message is transacted, the device sets the rtrt bit in the receive subaddress message information word in the subaddress data buffer. an rt-rt command pair where command word 2 is solely addressed to the HI-6130/21 terminal (not rt31) is con - sidered an rt-rt transmit command. the message information word does not distinguish the rt to rt transmit message from an ordinary rt to bc transmit command. 19.2. command illegalization table the following pages describe various structures residing in the ram shared between the host and HI-6130 or hi-6131 command processing logic. the host initializes these structures to control the terminals response to received com - mands. the frst structure described is the command illegalization table used for illegal command detection. illegal command detection is an optional process. when illegal command detection is not used, the terminal responds in form to all valid commands: it sends clear status and transacts the number of data words defned in the received command. when illegal command detection is not used, the bus controller cannot tell whether the command is legal or illegal, from the terminals transmitted response. if illegal command detection is used, the terminal responds differently when an illegal command is detected. the termi - nal responds to illegal commands with message error status, transmitting only status word. data word transmission is suppressed if the command type inherently includes transmitted data words. the terminal responds to each legal command with clear status and transacts the number of data words defned in the type of command received. for consistency, apply illegal command detection to all illegal and unimplemented commands, and to all reserved or undefned mode code commands, or respond in form to all of these commands (illegal command detection disabled) by leaving the illegalization table in the all-cleared default state after mr master reset the device uses a 256-word illegalization table in shared ram to distinguish between legal and illegal commands. after the ( mr ) master reset input is negated, HI-6130/31 performs internal self test including a shared ram test which HI-6130, hi-6131
holt integrated circuits 164 leaves all memory locations fully reset. once self test is complete, the HI-6130/31 ready output goes high to indicate HI-6130/31 readiness for host initialization. at this point, all entries in the illegalization table read logic 0, so by default, illegal command detection is not applied. to apply illegal command detection, the host (or auto-initialization) writes the illegalization table to set bits for all illegal command combinations. this typically includes any unimplemented subaddresses and/or word counts, undefned mode commands, reserved mode commands and any mode commands not implemented in the terminal design. host initialization of the table can be replaced by auto-initialization. once stex is set in the rt confguration register, terminal execution begins. each time a valid command is received, a 1-bit entry (indexed using command word data bits) is fetched from the illegalization table: if fetched illegalization table bit equals logic 0, the command is legal; the terminal responds in form, transmit - ting clear status and transacting the number of data words defned for the message type. terminal status is updated. if fetched illegalization table bit equals logic 1, the command is illegal; the terminal responds with status word only, with message error bit set. no data words are transmitted. terminal status is updated. when illegal command detection is not applied, all table entries should read logic 0; the terminal responds in form to all valid commands. the illegalization scheme allows any subset of command t/ r bit, broadcast vs. non-broadcast status, subaddress and word count (or mode code number), for a total of 4,096 legal/illegal command combinations. commands may be illegalized down to the word count level. for example, 10-word receive commands to a given subaddress may be legal, while 9-word receive commands to the same subaddress are illegal. broadcast receive commands are illegalized separately from non-broadcast receive commands. transmit and receive commands for the same subaddress are illegalized separately. for mode commands, any combination of mode code number, t/ r bit and broadcast/non-broadcast status can be legal or illegal. the illegalization table is located in shared ram within the fxed address range of 0x0200 to 0x02ff for rt1 and 0x0300 to 0x03ff for rt2. see figure 13 . the table is comprised of 256 16-bit words. to cover the full range of 1 to 32 data words, each subaddress uses a pair of illegalization registers. the lower register (even memory address) covers word counts 0 to 15, using one bit per word count. as in command encoding, 0 denotes 32 data words. bit 0 corresponds to 32 data words, bit 1 corresponds to 1 data word and bit 15 corresponds to 15 data words. the upper register (odd memory address) similarly covers word counts 16 to 31, using one bit per word count. bit 0 corresponds to 16 data words, while bit 15 corresponds to 31 data words. when a commands subaddress feld equals 0 or 31 (0x1f), the command is a mode command. table entries for mode commands use bits to represent mode code numbers, not word counts. the lower register (even memory address) covers mode codes 0 to 15, using one bit per mode code. bit 0 corresponds to mode code 0, bit 15 corresponds to mode code 15. the upper register (odd memory address) similarly covers mode codes 16 to 31, using one bit per mode code. bit 0 corresponds to mode code 16, bit 15 corresponds to mode code 31. there is no functional difference between sa0 mode commands and sa31 mode commands. since either subaddress indicates a mode command, the subaddress 0 table words should match the subaddress 31 table words in each quadrant. rt1 table entries from 0x0242 to 0x027d and rt2 table entries from 0x0342 to 0x037d do not have to be pro - grammed. these correspond to broadcast transmit subaddress commands (undefned by mil-std-1553b) and are always invalid. there is no terminal response. addressing for the illegalization table is derived from the command word t/ r bit, subaddress feld, msb of the word count (mode code) feld and the commands broadcast vs. non-broadcast status as shown below in figure 13 . HI-6130, hi-6131
holt integrated circuits 165 terminal address ta4:0 subaddress sa4:0 word count (mode code) wc4:0 t/ bi t r 00000001 ?0? if ta4:0 = 11111 else ?1? wc4 t/r sa4 sa3 sa2 sa1 sa0 table address bit fields comprise each received command word p command sync figure 13. deriving the illegalization table address from the received command word figure 15 on page 167 shows individual bit locations in the illegalization table for broadcast and non-broadcast variants of all mode commands defned by mil-std-1553b. locations are also identifed for reserved mode codes and unde - fned mode code commands. the following examples illustrate how the illegalization table is initialized to distinguish between legal and illegal com - mands when illegal command detection is being used. remember: if the terminal does not use illegal command detection, the table is left in its post- mr reset state, with all table locations reset to 0x0000. in this case, all command responses are in form. for subaddress commands (ordinary receive commands or transmit commands) individual table bits correspond to word counts specifed in the received command word. if a bit is 0, the corresponding word count is legal. if a bit is 1, the corresponding word count is illegal. for example, transmit commands to rt1 subaddress 1 are controlled by the words at 0x02c2 and 0x02c3. in figure 14 , these words are located in the rt address transmit block. the word stored at 0x02c3 controls subaddress 1 transmit commands having word counts 16 to 31. the word stored at 0x02c2 controls subaddress 1 transmit com - mands having word counts 1 to 15 or 32. (reminder: in mil-std-1553b, zero corresponds to 32 words.) word at 0x02c3 (tx subaddr 1) 31 to 16 words bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 words 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 word at 0x02c2 (tx subaddr 1) 15 to 1 & 32 words bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 32 if the word stored at 0x02c3 = 0xffff and the word stored at 0x02c2 = 0xff0f, then commands with 4, 5, 6, or 7 data words are the only legal transmit commands for subaddress 1 and all other word counts are illegal. receive com - mands and broadcast receive commands for subaddresses1 through 30 are encoded similarly. for mode code commands (characterized by command word subaddress feld equal to 00000 or 11111 binary) individual table bits correspond to individual mode code values. here transmit and receive simply indicate the state of the command word t/ r bit. (for mode codes 0-15, the t/ r bit does not indicate data direction since data is not transacted when fulflling these commands). HI-6130, hi-6131
holt integrated circuits 166 rt address tx mode codes 15 -0 rt address tx mode codes 31 -1 6 0x02c1 (0x03c1) 0x02c0 (0x03c0) rt address rx mode codes 15 -0 rt address rx mode codes 31 -1 6 0x0281 (0x0381) 0x0280 (0x0380) broadcast tx mode codes 15 -0 broadcast tx mode codes 31 -1 6 0x0241 (0x0341) 0x0240 (0x0340) broadcast rx mode codes 15 -0 broadcast rx mode codes 31 -1 6 0x0201 (0x0301) 0x0200 (0x0300) rt1 (rt2) 0x023f (0x033f) 0x0240 (0x0340) 0x027f (0x037f) 0x0280 (0x0380) 0x02bf (0x03bf) 0x02c0 (0x03c0) 0x02ff (0x03ff) broadcast transmit quadrant 32 subaddress blocks of 2 words each sa1 to sa30 are illegal broadcast transmit! rt addr tx sa30 w ord counts 15 -0 * rt address tx mode codes 15 -0 rt addr tx sa30 w ord counts 31 -1 6 rt address tx mode codes 31 -1 6 0x02ff (0x03ff) 0x02fe (0x03fe) 0x02fd (0x03fd) 0x02fc (0x03fc) example subaddress blocks from each table quadrant illegalization table comprised of 32 2-word blocks per quadrant rt address transmit quadrant 32 subaddress blocks of 2 words each 0x02bf (0x03bf) 0x02be (0x03be) 0x02bd (0x03bd) 0x02bc (0x03bc) 0x027f (0x037f) 0x027e (0x037e) 0x027d (0x037d) 0x027c (0x037c) 0x023f (0x033f) 0x023e (0x033e) 0x023d (0x033d) 0x023c (0x033c) rt addr rx sa30 w ord counts 15 -0* rt address rx mode codes 15 -0 rt addr rx sa30 w ord counts 31 -1 6 rt address rx mode codes 31 -1 6 broadcast tx sa30 w ord counts 15 -0 * broadcast tx mode codes 15 -0 broadcast tx sa30 w ord counts 31 -1 6 broadcast tx mode codes 31 -1 6 broadcast rx sa30 w ord counts 15 -0 * broadcast rx mode codes 15 -0 broadcast rx sa30 w ord counts 31 -1 6 broadcast rx mode codes 31 -1 6 tx subaddress 31 block (mode codes) tx subaddress 30 block tx subaddress 1 block tx subaddress 0 block (mode codes) rt address receive quadrant 32 subaddress blocks of 2 words each rx subaddress 31 block (mode codes) rx subaddress 30 block rx subaddress 1 block rx subaddress 0 block (mode codes) command sync tx subaddress 31 block (mode codes) tx subaddress 30 block tx subaddress 1 block tx subaddress 0 block (mode codes) rx subaddress 31 block (mode codes) rx subaddress 30 block rx subaddress 1 block rx subaddress 0 block (mode codes) broadcast receive quadrant 32 subaddress blocks of 2 words each * word count = 0 denotes 32 words * word count = 0 denotes 32 words * word count = 0 denotes 32 words * word count = 0 denotes 32 words 0x0200 (0x0300) rt1 (rt2) figure 14. address mapping for illegalization table note: rt1 table default start address is 0x0200. rt2 table default start address is 0x0300 HI-6130, hi-6131
holt integrated circuits 167 figure 15 summarizes the 16 illegalization table locations for mode commands. these locations are scattered throughout the overall illegalization table shown in figure 13. remember: the host must initialize all table locations corresponding to both subaddress 0 and subaddress 31 (11111 binary). consider an example for rt1 in which all reserved and all undefned mode commands are illegal. if all rt1 defned transmit mode commands are legal except mc0 (dynamic bus control) the eight table entries for transmit mode commands would be: 0x02ff and 0x02c1 = 1111 1111 1111 0010 = 0xfff2 0x02fe and 0x02c0 = 1111 1110 0000 0001 = 0xfe01 0x027f and 0x0241 = 1111 1111 1111 1111 = 0xffff 0x027e and 0x0240 = 1111 1110 0000 0101 = 0xfe05 the receive mode command words are encoded similarly. continuing the same example where all reserved and all undefned mode commands are illegal: if all rt1 defned receive mode commands are legal, the eight table entries for receive mode commands would be: 0x02bf and 0x0281 = 1111 1111 1100 1101 = 0xffcd 0x02be and 0x0280 = 1111 1111 1111 1111 = 0xffff 0x023f and 0x0201 = 1111 1111 1100 1101 = 0xffcd 0x023e and 0x0200 = 1111 1111 1111 1111 = 0xffff tx mc31- mc1 6 tx mc1 5-mc0 rx mc3 1- mc1 6 rx mc1 5- mc0 br .tx mc3 1-mc1 6 br .tx mc1 5- mc0 br .rx mc3 1- mc1 6 t ransmit mode commands with data receive mode commands with data t ransmit mode commands without data receive mode commands without data broadcast t ransmit mode commands with data broadcast receive mode commands with data broadcast t ransmit mode commands without data br .rx mc1 5- mc0 broadcast receive mode commands without data 0x02ff and 0x02c 1 0x02fe and 0x02c 0 0x02bf and 0x0281 0x02be and 0x0280 0x027f and 0x0241 0x027e and 0x0240 0x023f and 0x0201 0x023e and 0x0200 bit no. 15 14 13 12 11 10 9876543210 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 rrrrrrrrrruuddud 15 14 13 12 11 10 9876543210 rrrrrrrddddddddd 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 s rrrrrrrrrrdduudu 15 14 13 12 11 10 9876543210 uuuuuuuuuuuuuuuu d= defined mode command r= reserved mode code u= undefined mode command nb = defined code, but broadcast not allowed mc # status mc # status mc # stat u mc # status legend 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 rrrrrrrrrruu nb nb un b 15 14 13 12 11 10 9876543210 rrrrrrrdddddd nb dn b 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 rrrrrrrrrrdduudu 15 14 13 12 11 10 9876543210 uuuuuuuuuuuuuuuu mc # status mc # status mc # status mc # status ram address figure 15. summary of rt1 illegalization table addresses for mode code commands note: rt2 is the same except the table starts at 0x0300 instead of 0x0200. HI-6130, hi-6131
holt integrated circuits 168 19.3. temporary receive data buffer the 32-word temporary receive data buffer resides in shared ram in address space 0x01c0 to 0x01df for rt1 and 0x01e0 to 0x01ff for rt2. the device optionally uses this buffer for temporary storage of receive data words until successful message completion. to enable the buffer, the host asserts the trxdc bit in the rt1 or rt2 confguration register described in section 18.1 . when enabled, the terminal stores received data words in the 32-word buffer during message processing. upon error- free message completion, all buffered words are written in a burst to the data buffer memory assigned to the specifc subaddress in the rt1 or rt2 descriptor table. when the trxdb bit in the rt1 or rt2 confguration register is negated, the temporary receive data buffer is dis - abled. at 20us intervals, the terminal writes received data words to assigned subaddress data buffer memory as each word is received. if message error occurs during data reception, data integrity is lost; valid data from the prior receive message may be partially overwritten by data from a message ending in error. mil-std-1553 states that all received data from messages ending in error should be disregarded. in a typical application, the temporary buffer is not directly accessed by the host, although there is no restriction pre - venting host data access. the host should never write data into the temporary buffer space. 19.4. descriptor table the descriptor table, resides in shared ram, at default address ranges 0x0400 to 0x05ff for rt1 and 0x0600 to 0x07ff for rt2. this table is initialized by the host (or auto-initialization) to defne how the terminal processes valid commands. descriptor table settings for each command specify where message data is stored, how data is stored, whether host interrupts are generated, and other aspects essential to command processing. before initializing the ram descriptor table, the rt enable input pin rt1ena or rt2ena must be asserted and the corresponding rtxena bit must be set in the master confguration register 0x0000. terminal execution does not begin until the rt1stex or rt2stex bits are set in 9.1. master confguration register (0x0000) . shown in figure 16 , the table consists of 128 consecutive descriptor blocks, each comprised of four 16-bit words. the table is organized into four quadrants. the receive subaddress and transmit subaddress quadrants defne response for commands having a subaddress feld ranging from 1 to 30 (0x1e). these are simple n-data word receive or transmit commands, where n can range from 1 to 32 words. when the command t/ r bit equals 0, the receive command quadrant applies. when the t/ r bit equals 1, the transmit command quadrant applies. both subaddress quadrants are padded at top and bottom with unused descriptor blocks for subaddresses 0 and 31 (0x1f). the word space reserved for sa0 and sa31 aligns the table addressing, but values stored in these eight loca - tions is not used. command subaddresses 0 and 31 indicate mode commands. the response for commands contain - ing either sa value is defned in the two mode command table quadrants. the receive mode command quadrant applies when the command word t/ r bit equals 0, while the transmit mode command quadrants applies when t/ r equals 1. the term transmit mode command is misleading. all defned mode commands with mode code less than 0x0f havet/ r bit equal to 1, yet none of these mode commands transmits a data word. they transmit only the terminal sta - tus word, just like receive commands. however, the rt responds to transmit mode commands with mode code 0x10 to 0x1f by transmitting a mode data word. just three such transmit mode commands are defned. within the receive and transmit mode command quadrants, block addressing is based on the low order 5 bits in the command word, containing the mode code value. this is fundamentally different from the subaddress quadrants in which block addressing is based on the 5-bit subaddress feld. figure 17 shows how to derive control word address from the received command word. the control word address for the last valid command can also be found in the current control word address register. HI-6130, hi-6131
holt integrated circuits 169 all 128 4-word descriptor blocks start with a control word. there are four control word variants based on command type: receive vs. transmit and mode vs. non-mode commands. all descriptor control words are initialized by the host (or auto-initialization) to defne basic command response. each control word specifes the data buffer method and host interrupt for a specifc subaddress or mode command. each subaddress has both a receive subaddress block and a transmit subaddress block. receive and transmit com - mands to the same subaddress can be programmed to respond differently. the function of the three remaining descriptor words (in each 4-word block) depends on which of the 4 data buffer methods are specifed in the control word. indexed (or single buffer) method where a predetermined number of messages is transacted using a single data buffer in shared ram. several host interrupt options are offered, including an interrupt generated when all n messages are successfully completed. double (or ping-pong) buffer method where successive messages alternate between two data buffers in shared ram. several host interrupt options are offered. circular buffer mode 1 where buffer boundaries determine when the bulk transfer is complete and message informa - tion and time-tag words are stored with message data in a common buffer. several host interrupt options are offered, including an interrupt generated when the allocated data buffer is full. circular buffer mode 2 where the number of messages transacted defnes bulk transfer progress, and message data words are stored contiguously in one buffer while message information and time-tag words are stored in a separate buffer. several host interrupt options are offered, including an interrupt generated when all n messages are success - fully completed. the 4-word descriptor table entry for each command (its descriptor block) begins with a control word. there are four types of descriptor control word: ? receive subaddress control word ? transmit subaddress control word ? receive mode command control word ? transmit mode command control word the descriptor control word is initialized by the host to select data buffer method and interrupt options. after a com - mand is processed by the HI-6130/31 terminal, the device updates the commands descriptor control word. update will differ based on the chosen data buffer method. reading the descriptor table can differ from other ram accesses. for HI-6130, see section 25.1.1 . for hi-6131, see sections 25.2.6 and 25.2.8 . HI-6130, hi-6131
holt integrated circuits 170 0x05ff 0x0580 0x057f 0x0500 0x04ff 0x0480 0x047f 0x0400 subaddress 0 block 32 descriptor blocks of 4 words each transmit mode code quadrant (mode codes with t/r bit = 1) mode code 30 block control w ord for tx mc3 0 descriptor w ord3 for tx mc3 0 descriptor w ord2 for tx mc3 0 descriptor w ord4 for tx mc3 0 control w ord for rx mc3 0 descriptor w ord3for rx mc3 0 descriptor w ord2for rx mc3 0 descriptor w ord4for rx mc3 0 control w ord for tx sa30 descriptor w ord3 for tx sa30 descriptor w ord2 for tx sa30 descriptor w ord4 for tx sa30 control w ord for rx sa30 descriptor w ord3for rx sa30 descriptor w ord2for rx sa30 descriptor w ord4for rx sa30 0x05fb 0x05f a 0x05f9 0x05f8 0x057b 0x057a 0x0579 0x0578 0x04fb 0x04f a 0x04f9 0x04f8 0x047b 0x047a 0x0479 0x0478 example 4-word descriptor blocks from each table quadrant 32 4-word blocks per quadrant note: sa0 and sa31 indicate mode codes, so are not valid receive or transmit subaddresses. see note. see note. see note. see note. subaddress 1 block subaddress 30 block subaddress 31 block subaddress 0 block subaddress 1 block subaddress 30 block subaddress 31 block mode code 31 block mode code 0 block mode code 1 block mode code 30 block mode code 31 block mode code 0 block mode code 1 block 32 descriptor blocks of 4 words each receive mode code quadrant (mode codes with t/r bit = 0) 32 descriptor blocks of 4 words each transmit subaddress quadrant 32 descriptor blocks of 4 words each receive subaddress quadrant figure 16. address mapping for rt1 descriptor table note: assumes default table base address = 0x0400. rt2 is the same with default base address 0x0600. before initializing the rt1 or rt2 descriptor table, input pin rt1ena or rt2ena must be asserted and the rt1ena or rt2ena bit must be set in master confguration register 0x0000. HI-6130, hi-6131
holt integrated circuits 171 descriptor address format depends on command word?s subaddress 0000001 t/r sa4 sa3 sa2 sa1 sa0 p 00 descriptor table address for subaddress commands sa4:0 equals 00001 to 11110 0 0x0 0x2 0000001 t/r mc 4 mc 3 mc2 mc1 mc 0 p 00 1 0x0 0x3 rt addr ta4:0 subaddress sa4:0 word count wc4:0 t/ bi t r command sync rt addr ta4:0 subaddress sa4:0 mode code mc4:0 t/ bi t r command sync descriptor table address for mode code commands sa4:0 equals 00000 or 11111 figure 17. deriving a descriptor table control word address from command word (assumes table base address = 0x0200) 19.4.1. receive subaddress control word receive subaddress control words apply when a valid command word t/ r bit equals zero (receive) and the subaddress feld has a value in the range of 1 to 30 (0x1e). the descriptor control word defnes terminal command response and interrupt behavior, and conveys activity status to the host. it is initialized by the host before terminal execution begins. if using ping-pong data buffers, control words should only be written when the applicable rt1ena or rt2ena input pin is asserted and the corresponding rt1ena or rt2ena bit is also set in the master confguration register 0x0000. failure to meet this requirement prevents automatic assertion of ppon bit 8 when ppen bit 2 is set, and successive messages will repeatedly use the same buffer. bits 8-11 cannot be written by the host; these bits are updated by the device during terminal execution, that is, when the rt confguration register stex bit equals 1. the host can write bits 0-2 and 4-7 only when stex equals zero; bits 3 and 12-15 can be written anytime. this register is cleared to 0x0000 by mr master reset. software reset (srst) clears just the dbac, dpb and bcast bits. following any read cycle to the control word address, the dbac bit is reset. msb lsb 15 14 13 12 11 10 9876543210 dbac iwa bcast cir2zn3 cir2zn2 cir2zn0 stopp ppen cir2en cir1en ixeqz cir2zn1 ppon mkbusy dpb d1 ddd h hhhhhhhh ibr h bit set by device, reset by host read cycle d d1 bit maintained by host h bit maintained by device h h note: reset refers to bit value following master reset ( mr ). the bit value following software reset is un - changed unless specifcally indicated by an sr value. bit no. mnemonic r/w reset function 15 ixeqz 0 interrupt when index equals zero. if the interrupt enable register ixeqz bit is high, assertion of this bit enables generation of an interrupt for (a) subaddresses using indexed buffer mode when the indx value decrements from 1 to 0, or (b) subaddresses using a circular buffer mode when the pre-determined number of messages has been transacted. if enabled, upon completion of command processing that results in index = 0, an ixeqz interrupt is entered in the pending interrupt register, output pin int is asserted, and the interrupt is registered in the interrupt log. HI-6130, hi-6131
holt integrated circuits 172 bit no. mnemonic r/w reset function 14 iwa 0 interrupt when accessed. if the interrupt enable register iwa bit is high, assertion of this bit enables interrupt generation when the subaddress receives any valid receive com - mand. if enabled, upon completion of command processing, an iwa interrupt is entered in the pending interrupt register, output pin int is asserted, and the interrupt is registered in the interrupt log. 13 ibr 0 interrupt broadcast received. if the interrupt enable register ibr bit is high, assertion of this bit enables in - terrupt generation when the subaddress receives a valid broadcast command. if enabled, upon completion of message processing an ibr interrupt is entered in the pending interrupt register, output pin int is asserted, and the interrupt is registered in the interrupt log. this bit has no function if the bcstinv bit is high in the rt confguration register. in this case, commands to rt address 31 are not recognized as valid by the device. 12 mkbusy 0 make busy. the host asserts the mkbusy bit to respond with busy status for commands to this receive subaddress. this bit is an alternative to globally applying busy status for all valid commands, enabled from the 1553 status bits register. see that register description for additional information. when busy is asserted, received data words are not stored and the dpb bit does not toggle after mes - sage completion. 11 dbac 0 sr = 0 descriptor block accessed. internal device logic asserts the dbac bit upon completion of message processing. the host may poll this bit to detect subaddress activity, instead of using host interrupts. this bit is reset to logic 0 by mr master reset, srst software reset or a read cycle to this memory address. 10 dpb 0 sr = 0 data pointer b. this status bit is maintained by the device and only applies in ping-pong buffer mode. this bit indicates the buffer to be used for the next occurring receive command to this subaddress. when the dpb bit is logic 0, the next message will use data pointer a; when dpb is logic 1, the next message uses data pointer b. in ping-pong buffer mode, the bit is inverted after each error-free message completion. the dpb bit is not altered after messages ending in er - ror, after illegal commands or after messages when the terminal responds with busy status. this bit is reset to logic 0 by mr master reset or srst software reset; therefore the frst message received after either reset will use buf fer a. this bit is dont care for indexed single-buffer mode or either circular buffer mode. 9 bcast 0 sr = 0 broadcast command. device logic sets this bit when a valid broadcast receive command is received at this subaddress. if ibr bit 13 and interrupt enable register ibr bit are both set, the output pin int is asserted. this bit has no function if the bcstinv bit is asserted in the the rt confguration register; in this case commands to rt address 31 are not recognized as valid by the device. this bit is reset to logic 0 by mr master reset or srst software reset. HI-6130, hi-6131
holt integrated circuits 173 bit no. mnemonic r/w reset function 8 ppon 0 ping-pong enable acknowledge. this bit is controlled by the device and cannot be written by the host. it only applies if ppen bit 2 was initialized to logic one by the host after reset, en - abling ping-pong buffer mode for this subaddress. device logic asserts this bit when it recognizes ping-pong is active for this subaddress. before off-loading the receive data buffer for this subaddress, the host can ask the device to temporarily disable ping-pong by asserting stopp bit 3. the device acknowl - edges ping-pong is disabled by negating ppon. the host can safely off-load the buffer without data collision while ppon is negated. after buffer servicing, the host asks the device to re-enable ping-pong by negating stopp bit 3. the device acknowledges ping-pong is re-enabled by asserting ppon. if ppen bit 2 is high and ppon bit 8 is low when new commands arrive for this subaddress, ping-pong is disabled. each new message overwrites exist - ing data in the buffer specifed by dpb bit 10, and the dpb bit does not toggle after command completion. 7-4 cir2zn 0 circular mode 2 zero number. used only in circular buffer mode 2, this 4-bit feld is initialized with the number of trailing zeros in the initialized miba address. this is explained in section 20.6 , which fully describes circular buffer mode 2. 3 stopp 0 stop ping-pong request. the host asserts this bit to suspend ping-pong buffering for this subaddress. the host resets this bit to ask the device to re-enable ping-pong. the device confrms recognition of ping-pong enable or disable status by writing ppon bit 8. refer to section 20.3 , which fully describes ping-pong mode. 2 1 0 ppen cir2en cir1en 0 0 0 ping-pong, circular buffer mode 2 or circular buffer mode 1 enable. the ppen, cir2en and cir1en bits are initialized by the host to select buffer mode. the table below summarizes how buffer mode selection is encoded. in the case of ping-pong, the host initializes the ppen bit to logic one after reset to enable ping-pong buffering for this subaddress. the host asserts stopp bit 3 to ask the device to temporarily disable ping-pong. negating the stopp bit asks the device to re-enable ping-pong. the device confrms ping- pong enable or disable state changes by writing the ppon bit. ppen bit 2 should only be initialized or otherwise written when the applicable rt1ena or rt2ena input pin is asserted, and the corresponding rt1ena or rt2ena bit is also set in the master confguration register 0x0000. ppen cir2en cir1en buffer mode 1 dont care dont care ping-pong 0 1 dont care circular mode 2 0 0 1 circular mode 1 0 0 0 indexed single buffer HI-6130, hi-6131
holt integrated circuits 174 19.4.2. transmit subaddress control word transmit subaddress control words apply when a valid command word t/ r bit equals one (transmit) and the subaddress feld has a value in the range of 1 to 30 (0x1e). the descriptor control word defnes terminal command response and interrupt behavior, and conveys activity status to the host. it is initialized by the host before terminal execution begins. if using ping-pong data buffers, control words should only be written when the applicable rt1ena or rt2ena input pin is asserted and the corresponding rt1ena or rt2ena bit is also set in the master confguration register 0x0000. failure to meet this requirement prevents automatic assertion of ppon bit 8 when ppen bit 2 is set, and successive messages will repeatedly use the same buffer. bits 8-11 cannot be written by the host; these bits are updated by the device during terminal execution, that is, when the rt confguration register stex bit equals 1. the host can write bits 0-2 and 4-7 only when stex equals zero; bits 3,12 and 14-15 can be written anytime. this register is cleared to 0x0000 by mr master reset. software reset (srst) clears just the dbac, dpb and bcast bits. following any host read cycle to the control word address, the dbac bit is reset. msb lsb 15 14 13 12 11 10 9876543210 x dbac iwa bcast cir2zn3 cir2zn2 cir2zn0 stopp ppen cir2en cir1en ixeqz cir2zn1 ppon mkbusy dpb d1 ddd h hh hhhhhhhh bit is not used, may be logic 0 or 1 x bit set by device, reset by host read cycle d d1 bit maintained by host h bit maintained by device note: reset refers to bit value following master reset ( mr ). the bit value following software reset is un - changed unless specifcally indicated by an sr value. bit no. mnemonic r/w reset function 15 ixeqz 0 interrupt when index equals zero. if the interrupt enable register ixeqz bit is high, assertion of this bit enables generation of an interrupt for (a) subaddresses using indexed buffer mode when the indx value decrements from 1 to 0, or (b) subaddresses using a circular buffer mode when the pre-determined number of messages has been transacted. if enabled, upon completion of command processing that results in index = 0, an ixeqz interrupt is entered in the rt pending interrupt reg - ister, output pin int is asserted, and the interrupt is registered in the interrupt log. 14 iwa 0 interrupt when accessed. if the interrupt enable register iwa bit is high, assertion of this bit enables interrupt generation when the subaddress receives any valid transmit com - mand. if enabled, upon completion of command processing, an iwa interrupt is entered in the rt pending interrupt register, output pin int is asserted, and the interrupt is registered in the interrupt log. 13 ----- 0 not used 12 mkbusy 0 make busy. the host asserts the mkbusy bit to respond with busy status for commands to this transmit subaddress. this bit is an alternative to globally applying busy status for all valid commands, enabled from the 1553 status bits register. see that register description for additional information. when busy is as - serted, data words are not transmitted and the dpb bit does not toggle after message completion. HI-6130, hi-6131
holt integrated circuits 175 bit no. mnemonic r/w reset function 11 dbac 0 sr = 0 descriptor block accessed. internal device logic asserts the dbac bit upon completion of message processing. the host may poll this bit to detect subaddress activity, instead of using host interrupts. this bit is reset to logic zero by mr master reset, srst software reset or a read cycle to this memory address. 10 dpb 0 sr = 0 data pointer b. this status bit is maintained by the device and only applies in ping-pong buffer mode. this bit indicates the buffer to be used for the next occurring transmit command to this subaddress. when the dpb bit is logic 0, the next message will use data pointer a; when dpb is logic 1, the next message uses data pointer b. in ping-pong buffer mode, the bit is inverted after each error-free message completion. the dpb bit is not altered after messages ending in error, after illegal commands or after messages when the terminal responds with busy status. this bit is reset to logic 0 by mr master reset or srst software reset; therefore the frst message received after either reset will use buffer a. this bit is dont care for indexed single-buffer mode or either circular buffer mode. 9 bcast 0 sr = 0 broadcast received. the device sets this bit when a broadcast-transmit command is received for this subaddress. because non-mode broadcast-transmit commands are always illegal, the assertion of this bit in the control word by the device indi - cates an illegal command was received. terminal response varies, depending on whether or not illegal command detection applies (any bits set in illegal - ization table). this bit has no function if the bcstinv bit is asserted in the rt confguration register; in this case commands to rt address 31 are not recognized as valid by the device. this bit is reset to logic 0 by mr master reset or srst software reset. 8 ppon 0 ping-pong enable acknowledge. this bit is controlled by the device and should not be written by the host. it only applies if ppen bit 2 was initialized to logic one by the host after reset, enabling ping-pong buffer mode for this subaddress. the rt asserts this bit when it recognizes ping-pong is active for this subaddress. before load - ing the transmit data buffer for this subaddress, the host can ask the rt to temporarily disable ping-pong by asserting stopp bit 3. the rt acknowl - edges ping-pong is disabled by negating ppon. the host can safely load the buffer without data collision while ppon is negated. after buffer servicing, the host asks the rt to re-enable ping-pong by negating stopp bit 3. the rt acknowledges ping-pong is re-enabled by asserting ppon. if ppen bit 2 is high and ppon bit 8 is low when new commands arrive for this subaddress, ping-pong is disabled. each new message transmits data from the same buffer, specifed by dpb bit 10, and the dpb bit does not toggle after command completion. 7-4 cir2zn 0 circular mode 2 zero number. used only in circular buffer mode 2, this 4-bit feld is initialized with the number of trailing zeros in the initialized miba address. this is explained in section 20.6 , which fully describes circular buffer mode 2. HI-6130, hi-6131
holt integrated circuits 176 bit no. mnemonic r/w reset function 3 stopp 0 stop ping-pong request. the host asserts this bit to suspend ping-pong buffering for this subaddress. the host resets this bit to ask the rt to re-enable ping-pong. the rt con - frms recognition of ping-pong enable or disable status by writing ppon bit 8. refer to section 20.3 , which describes ping-pong mode in detail. 2 1 0 ppen cir2en cir1en 0 0 0 ping-pong, circular buffer mode 2 or circular buffer mode 1 enable. the ppen, cir2en and cir1en bits are initialized by the host to select buffer mode. the table below summarizes how buffer mode selection is encoded. in the case of ping-pong, the host initializes the ppen bit to logic one after reset to enable ping-pong buffering for this subaddress. the host asserts stopp bit 3 to ask the device to temporarily disable ping-pong. negating the stopp bit asks the device to re-enable ping-pong. the device confrms ping- pong enable or disable state changes by writing the ppon bit. ppen bit 2 should only be initialized or otherwise written when the applicable rt1ena or rt2ena input pin is asserted, and the corresponding rt1ena or rt2ena bit is also set in the master confguration register 0x0000. ppen cir2en cir1en buffer mode 1 dont care dont care ping-pong 0 1 dont care circular mode 2 0 0 1 circular mode 1 0 0 0 indexed single buffer 19.4.3. data buffer options for mode code commands data buffer options for mode code commands differ from options offered for subaddress commands. mode commands cannot use either circular data buffer method, but may use double (ping-pong) buffering or single (indexed) buffering. single message index mode (indx = 0) is suitable in many applications (see section 20.4.1 ). an alternative called simplifed mode command processing (smcp) may be globally applied for all mode code commands (see section 21.5 ). to use single (indexed) buffer or double (ping-pong) buffer for mode commands, the smcp bit in the rt confguration register is logic 0. the control word ppen bit for each mode command determines whether ping-pong or indexed buffering is used. to use simplifed mode command processing, the smcp bit in the rt confguration register is set to logic 1. the control word ppen bit for mode commands is dont care (no longer specifes index or ping-pong buffer mode) because simplifed mode command processing stores mode command data and message information words directly within each mode commands redefned descriptor table block. when smcp is enabled, mode code command descriptor blocks (in the descriptor table) do not contain data pointers to reserved buffers elsewhere in the shared ram. instead, each 4-word descriptor block itself contains the message information word, the time-tag word and the data word transacted for each mode command (for mode codes 16-31 decimal). when simplifed mode command processing is used, the range of active bits is reduced in each receive or transmit mode command control word. interrupt control and response is not affected by the smcp option. simplifed mode HI-6130, hi-6131
holt integrated circuits 177 command processing is fully presented in the later data sheet section 21.5 . 19.4.4. receive mode control word receive mode control words apply when the command word t/ r bit equals zero (receive) and the subaddress feld has a value of 0 or 31 (0x1f). the descriptor control word defnes terminal command response and interrupt behavior, and conveys activity status to the host. it is initialized by the host before terminal execution begins. if using ping-pong data buffers, control words should only be written when the applicable rt1ena or rt2ena input pin is asserted and the corresponding rt1ena or rt2ena bit is also set in the master confguration register 0x0000. failure to meet this requirement prevents automatic assertion of ppon bit 8 when ppen bit 2 is set, and successive messages will repeatedly use the same buffer. bits 8-11 cannot be written by the host; these bits are updated by the device during terminal execution, that is, when the rt confguration register stex bit equals 1. the host can write bit 2 only when stex equals zero; bits 3 and 12-15 can be written anytime. this register is cleared to 0x0000 by mr master reset. software reset (srst) clears just the dbac, dpb and bcast bits. following any read cycle to the control word address, the dbac bit is reset. when single-message indexed buffering or ping-pong buffering is used instead of smcp (simplifed mode code pro - cessing), the receive mode control word looks like this: msb lsb 15 14 13 12 11 10 9876543210 h dbac iwa bcast stopp ppen ixeqz ppon mkbusy dpb d1 h bit is not used, may be logic 0 or 1 x bit set by device, reset by host read cycle d d1 bit maintained by host h bit maintained by device ibr h h x x x x x h h x d d d when smcp applies, the number of active mode control word bits is reduced: msb lsb 15 14 13 12 11 10 9876543210 h dbac iwa bcast ixeqz ppon mkbusy d1 h bit is not used, may be logic 0 or 1 x bit set by device, reset by host read cycle d d1 bit maintained by host h bit maintained by device ibr h h x x x x x x x x d d x note: reset refers to bit value following master reset ( mr ). the bit value following software reset is un - changed unless specifcally indicated by an sr value. bit no. mnemonic r/w reset function 15 ixeqz 0 interrupt when index equals zero. if the interrupt enable register ixeqz bit is high, assertion of this bit enables generation of an interrupt for mode code commands using indexed buffer mode when the indx value decrements from 1 to 0. upon completion of command processing that results in indx = 0, when ixeqz interrupts are en - abled, an ixeqz interrupt is entered in the rt pending interrupt register, the int output pin is asserted, and the interrupt is registered in the interrupt log. HI-6130, hi-6131
holt integrated circuits 178 bit no. mnemonic r/w reset function 14 iwa 0 interrupt when accessed. if the interrupt enable register iwa bit is high, assertion of this bit enables interrupt generation at each instance of a valid mode code command. upon completion of command processing, when iwa interrupts are enabled, an iwa interrupt is entered in the rt pending interrupt register, the int output pin is asserted, and the interrupt is registered in the interrupt log. 13 ibr 0 interrupt broadcast received. if the interrupt enable register ibr bit is high, assertion of this bit enables interrupt generation at each instance of a valid broadcast receive mode code command. upon completion of command processing, when ibr interrupts are enabled, an ibr interrupt is entered in the pending interrupt register, the int output pin is asserted, and the interrupt is registered in the interrupt log. this bit has no function if the bcstinv bit is high in the rt confguration register. in this case, commands to rt address 31 are not recognized as valid by the device. 12 mkbusy 0 make busy. the host asserts the mkbusy bit to respond with busy status for commands to this mode code. this bit is an alternative to globally applying busy status for all valid commands, enabled from the rt 1553 status bits register. see that register description for additional information. when busy is asserted, mode data words received with mc16-mc31 are not stored and the dpb bit does not toggle after message completion. 11 dbac 0 sr = 0 descriptor block accessed. internal device logic asserts the dbac bit upon completion of message pro - cessing. the host may poll this bit to detect mode command activity, instead of using host interrupts. this bit is reset to logic 0 by mr master reset, srst software reset or a read cycle to this memory address. 10 dpb 0 sr = 0 data pointer b. this status bit is maintained by the device and only applies for mode com - mands using ping-pong buffer mode. this bit indicates the buffer to be used for the next occurring mode command. when the dpb bit is logic 0, the next message will use data pointer a; when dpb is logic 1, the next message uses data pointer b. in ping-pong buffer mode, the bit is inverted after each error-free message completion. the dpb bit is not altered after messages ending in error, after illegal commands, or after messages when the terminal responds with busy status. this bit is reset to logic 0 by mr master reset or srst software reset; therefore the frst message received after either reset will use buffer a. this bit is dont care for indexed single-buffer mode. 9 bcast 0 sr = 0 broadcast received. device logic sets this bit when a valid broadcast mode command is received having t/ r bit = 0. this bit has no function if the bcstinv bit is asserted in the rt confguration register. in this case, rt address 31 commands are not recognized as valid by the HI-6130/31. this bit is reset to logic 0 by mr master reset or srst software reset. HI-6130, hi-6131
holt integrated circuits 179 bit no. mnemonic r/w reset function 8 ppon 0 ping-pong enable acknowledge. this bit is read only and only applies for mode commands using ping-pong mode (ppen bit 2 was initialized to logic 1 by the host after reset). the device asserts this bit when it recognizes ping-pong is active for this mode code. before off-loading the receive data buffer for this mode code, the host can ask the device to temporarily disable ping-pong by asserting stopp bit 3. the device acknowledges ping-pong is disabled by negating ppon. the host can safely load or off-load the buffer without data collision while ppon is negated. after buffer servicing, the host asks the device to re-enable ping-pong by negating stopp bit 3. the device acknowledges ping-pong is re-enabled by asserting ppon. if ppen bit 2 is high and ppon bit 8 is low when new commands arrive for this subaddress, ping-pong is disabled. each new message overwrites existing data in the buffer specifed by dpb bit 10, and the dpb bit does not toggle after command completion. 7-4 ----- 0 not used 3 stopp 0 stop ping-pong request. the host asserts this bit to suspend ping-pong buffering for this mode code. the host resets this bit to ask the device to re-enable ping-pong. the device confrms recognition of ping-pong enable or disable status by writing ppon bit 8. 2 ppen 0 ping-pong buffer enable. the ppen bit is initialized by the host to select buffer mode. if this bit is high, ping-pong buffering is selected. if this bit is low, indexed single buffering is selected. after reset, the host initializes this bit to logic 1 to enable ping-pong buffering for this mode code. the host asserts stopp bit 3 to ask the device to temporarily disable ping-pong. negating the stopp bit asks the device to re-enable ping-pong. the device confrms ping-pong enable or disable state changes by writing the ppon bit 8. ppen bit 2 should only be initialized or otherwise written when the applicable rt1ena or rt2ena input pin is asserted, and the corresponding rt1ena or rt2ena bit is also set in the master confguration register 0x0000. 1,0 ----- 0 not used. 19.4.5. transmit mode control word transmit mode control words apply when the command word t/ r bit equals one (transmit) and the subaddress feld has a value of 0 or 31 (0x1f). the descriptor control word defnes terminal command response and interrupt behavior, and conveys activity status to the host. it is initialized by the host before terminal execution begins. if using ping-pong data buffers, control words should only be written when the applicable rt1ena or rt2ena input pin is asserted and the corresponding rt1ena or rt2ena bit is also set in the master confguration register 0x0000. failure to meet this requirement prevents automatic assertion of ppon bit 8 when ppen bit 2 is set, and successive messages will repeatedly use the same buffer. bits 8-11 cannot be written by the host; these bits are updated by the device during terminal execution, that is, when the rt confguration register stex bit equals 1. the host can write bit 2 only when stex equals zero; bits 3 and 12-15 can be written anytime. this register is cleared to 0x0000 by mr master reset. HI-6130, hi-6131
holt integrated circuits 180 software reset (srst) clears just the dbac, dpb and bcast bits. following any read cycle to the control word address, the dbac bit is reset. when single-message indexed buffering or ping-pong buffering is used instead of smcp (simplifed mode code processing), the transmit mode control word looks like this: msb lsb 15 14 13 12 11 10 9876543210 h dbac iwa bcast stopp ppen ixeqz ppon mkbusy dpb d1 h bit is not used, may be logic 0 or 1 x bit set by device, reset by host read cycle d d1 bit maintained by host h bit maintained by device ibr h h x x x x x h h x d d d when smcp applies, the number of active mode control word bits is reduced: msb lsb 15 14 13 12 11 10 9876543210 h dbac iwa bcast ixeqz ppon mkbusy d1 h bit is not used, may be logic 0 or 1 x bit set by device, reset by host read cycle d d1 bit maintained by host h bit maintained by device ibr h h x x x x x x x x d d x note: reset refers to bit value following master reset ( mr ). the bit value following software reset is un - changed unless specifcally indicated by an sr value. bit no. mnemonic rw reset function 15 ixeqz 0 interrupt when index equals zero. if the interrupt enable register ixeqz bit is high, assertion of this bit enables generation of an interrupt for mode code commands using indexed buffer mode when the indx value decrements from 1 to 0. upon completion of command processing that results in indx = 0, when ixeqz interrupts are en - abled, an ixeqz interrupt is entered in the rt pending interrupt register, the int output pin is asserted, and the interrupt is registered in the interrupt log. 14 iwa 0 interrupt when accessed. if the interrupt enable register iwa bit is high, assertion of this bit enables interrupt generation at each instance of a valid mode code command. upon completion of command processing, when iwa interrupts are enabled, an iwa interrupt is entered in the rt pending interrupt register, the int output pin is asserted, and the interrupt is registered in the interrupt log. 13 ibr 0 interrupt broadcast received. if the interrupt enable register ibr bit is high, assertion of this bit enables interrupt generation at each instance of a valid broadcast transmit mode code command. upon completion of command processing, when ibr interrupts are enabled, an ibr interrupt is entered in the rt pending interrupt register, the int output pin is asserted, and the interrupt is registered in the interrupt log. this bit has no function if the bcstinv bit is high in the rt confgura - tion register. in this case, commands to rt address 31 are not recognized as valid by the device. HI-6130, hi-6131
holt integrated circuits 181 bit no. mnemonic rw reset function 12 mkbusy 0 make busy. the host asserts the mkbusy bit to respond with busy status for commands to this mode code. this bit is an alternative to globally applying busy status for all valid commands, enabled from the rt 1553 status bits register. see that register description for additional information. when busy is asserted, mode data words are not transmitted with mc16-mc31, and the dpb bit does not toggle after message completion. the mkbusy bit is not heeded if set in the control word for mode code command mc8 reset remote terminal. for this command only, busy is inhibited for the status response transmitted before the reset process begins. 11 dbac 0 sr = 0 descriptor block accessed. internal device logic asserts the dbac bit upon completion of message pro - cessing. the host may poll this bit to detect mode command activity, instead of using host interrupts. this bit is reset to logic 0 by mr master reset, srst software reset or a read cycle to this memory address. 10 dpb 0 sr = 0 data pointer b. this status bit is maintained by the device and only applies for mode com - mands using ping-pong buffer mode. this bit indicates the buffer to be used for the next occurring mode command. when the dpb bit is logic 0, the next message will use data pointer a; when dpb is logic 1, the next message uses data pointer b. in ping-pong buffer mode, the bit is inverted after each error-free message completion. the dpb bit is not altered after messages ending in error, after illegal commands, or after messages when the terminal responds with busy status. this bit is reset to logic 0 by mr master reset or srst software reset; therefore the frst message received after either reset will use buffer a. this bit is dont care for indexed single-buffer mode. 9 bcast 0 sr = 0 broadcast received. device logic sets this bit when a valid broadcast mode command is received having t/ r bit = 1. this bit has no function if the bcstinv bit is asserted in the rt confguration register. in this case, rt address 31 commands are not recognized as valid by the HI-6130/31. this bit is reset to logic 0 by mr master reset or srst software reset. 8 ppon 0 ping-pong enable acknowledge. this bit is read only and only applies for mode commands using ping-pong mode (ppen bit 2 was initialized to logic 1 by the host after reset). the device asserts this bit when it recognizes ping-pong is active for this mode code. before loading the transmit data buffer for this mode code, the host can ask the device to temporarily disable ping-pong by asserting stopp bit 3. the device acknowledges ping-pong is disabled by negating ppon. the host can safely load or off-load the buffer without data collision while ppon is ne - gated. after buffer servicing, the host asks the device to re-enable ping-pong by negating stopp bit 3. the device acknowledges ping-pong is re-enabled by asserting ppon. if ppen bit 2 is asserted and ppon bit 8 is negated when a new command arrives for this mode code, ping-pong disable handshake is in effect: the device applies single-buffer index mode using data pointer a or data pointer b, per dpb bit 10. the dpb bit does not toggle after command completion. HI-6130, hi-6131
holt integrated circuits 182 bit no. mnemonic rw reset function 7-4 ----- 0 not used 3 stopp 0 stop ping-pong request. the host asserts this bit to suspend ping-pong buffering for this mode code. the host resets this bit to ask the device to re-enable ping-pong. the device confrms recognition of ping-pong enable or disable status by writing ppon bit 8. 2 ppen 0 ping-pong buffer enable. the ppen bit is initialized by the host to select buffer mode. if this bit is high, ping-pong buffering is selected. if this bit is low, indexed single buffering is selected. after reset, the host initializes this bit to logic 1 to enable ping-pong buffering for this mode code. the host asserts stopp bit 3 to ask the device to tempo - rarily disable ping-pong. negating the stopp bit asks the device to re-enable ping-pong. the device confrms ping-pong enable or disable state changes by writing the ppon bit 8. ppen bit 2 should only be initialized or otherwise written when the applicable rt1ena or rt2ena input pin is asserted, and the corresponding rt1ena or rt2ena bit is also set in the master confgu - ration register 0x0000. 1,0 ----- 0 not used. HI-6130, hi-6131
holt integrated circuits 183 20. remote terminal rt1 and rt2 message data buffers the memory structures described up to this point comprise not more than 2k words of the lower memory address space. the remaining memory is allocated by the host for message data storage, to fulfll application requirements. this section describes the remaining data structures in shared ram that control (and result from) command process - ing. by initializing the rt descriptor table, the host allocates memory space for storing data for each subaddress used in the remote terminal application. each legal receive subaddress and each legal transmit subaddress are usually assigned unique buffer memory spaces. (exception: to comply with the requirements for mil-std-1553 data wrap- around, it is convenient to assign the data wrap-around subaddress to use the same buffer space for both receive and transmit commands.) as an option, data from broadcast receive commands can be stored separately from data resulting from non-broadcast receive commands. each subaddress buffer can use any of four data storage methods offered. subaddress (non-mode) commands are transacted with one to 32 data words. these are stored in a data buffer in shared ram. for receive commands, the device stores data received during message processing in the shared ram buffer. later, the host retrieves these data words from the buffer. in the case of transmit commands, the host has previously stored transmit data words in the transmit subaddress buffer. the device retrieves these data words for transmission while processing the transmit command. for each complete message processed, the message data stored in the buffer is comprised of these elements: 1. message information word. 2. time-tag word. 3. one to 32 data words transmitted or received during message transaction ( except no data word for mode code commands 0 - 15 decimal). the message information word and time-tag word are generated by the device and stored in assigned buffer space to aid the host in further message processing. the message information word contains message type, word count and message error information. the 16-bit time-tag word contains the value in the device internal time-tag counter when the command is validated. the host initializes the descriptor table entry for each subaddress or mode command to select one of four data buffer - ing methods. 1. indexed (single buffer) method (see 20.4 ). a predetermined number of messages (n) is transacted using a single data buffer in shared ram. several host in - terrupt options are offered, including host interrupt when all n messages are successfully completed. this method also supports single-message mode when n is purposely initialized to zero. 2. double (or ping-pong) buffer method (see 20.3 ). successive messages alternate between two 34-word data buffers in shared ram. several host interrupt options are offered. 3. circular buffer mode 1 (see 20.5 ). buffer boundaries determine when the bulk transfer is complete. message information and time-tag words are stored in the same buffer with data words. several host interrupt options are offered, including host interrupt when the allocated data buffer is full. 4. circular buffer mode 2 (see 20.6 ). the number of messages transacted defnes bulk transfer progress. message data words are stored contiguously in one buffer while message information and time-tag words are stored in a separate buffer. several host interrupt options are offered, including host interrupt when all n messages are completed. HI-6130, hi-6131
holt integrated circuits 184 the data buffer options are summarized in table 15 . simplifed mode command processing. this is a global option that applies for all mode code commands, when enabled. mode commands have either one data word, or no data word. instead of using data buffers for storing this limited mode command data, the message data is stored directly within the descriptor table. this option for mode commands is described in section 21.5 . broadcast data separation when the notice2 option is enabled, data words resulting from broadcast receive commands will be stored separate - ly from data resulting from non-broadcast receive commands when using indexed or ping-pong buffer modes. when notice2 applies, all subaddresses using indexed or ping-pong modes must have an assigned 34-word broadcast data buffer in addition to the primary buffers listed above. broadcast data segregation cannot be done using either circular buffer mode. table 15. summary of data buffer modes. buffer mode data buffer(s) number and size message info word suitable for mode codes? primary application indexed one. host defnes size for n messages stored in same buffer as data yes, only single message mode for transacting n (multiple) messages with optional host interrupt when done ping-pong two 34-word buffers, one message each stored in same buffer as data yes for transacting single messages, alternating between a and b buffers circular 1 one. host defnes size for n words stored in same buffer as data no for transacting messages until buffer is full / empty, optional interrupt when done circular 2 one. host defnes size for n messages, plus msg info block stored in separate buffer (msg info block) no for transacting n (multiple) messages with optional host interrupt when done. data buffer holds contiguous pure data. 20.1. subaddress message information words 20.1.1. receive subaddress command for receive subaddress commands, the device stores the received data words plus two additional words. the device adds a receive subaddress message information word and a time-tag word to the received data words. the device stores the message information and time-tag words ahead of the data words associated with the receive command, as shown below. if message error occurs, the rt stores only the receive subaddress message information word and time-tag word. once a message error is detected, the device sets the merr bit in the receive subaddress message information word. when this occurs, all data words are considered invalid. whenever the receive subaddress mes - sage information word merr bit is set, the host should disregard the records data word(s). here is an example data structure for a 3-word receive command. notice that the receive subaddress data pointer points to the data structure starting address, not the frst data word. the data pointer is located in the receive subad - dress commands descriptor block, fully described later: HI-6130, hi-6131
holt integrated circuits 185 data buffer hex address word description device writes word ... data pointer equals 0x1500 0x1500 0x1501 0x1502 0x1503 0x1504 message information word time-tag word data word 1 data word 2 data word 3 after message completion after message completion (see note ) note: the data words are written after message completion when the rt confguration register bit trxdb is 1, otherwise written when received. synerr gaperr iwderr merr wcterr busid rtrt wc3 wc2 wc1 wc0 msb lsb 15 14 13 12 11 10 9876543210 wc4 ilcmd txrterr wasbsy tmoerr the following bits comprise the receive subaddress message information word: bit no. mnemonic function 15 tmoerr time-out error. this bit is asserted for rt-rt receive messages when the transmitting terminal fails to start its status word and data transmission before time-out occurs, per tosel0-1 bits in the rt confguration register. 14 iwderr invalid word error. assertion of this bit indicates manchester error or parity error was observed in a received data word. 13 gaperr gap error. assertion of this bit indicates bus activity was detected immediately after the last expected receive data word or that a gap occurred before all expected data words were received. 12 wcterr word count error. this bit is asserted if command is received with less data words than the command word specifes. for example, a receive command for three data words is received with two contiguous data words. 11 synerr sync error. this bit is asserted when an incorrect (command/status) sync type occurs in received data words. 10 merr message error. this bit is asserted when message error status change occurs during command process - ing. see bits 7 and 11-15 for details. HI-6130, hi-6131
holt integrated circuits 186 bit no. mnemonic function 9 wasbsy was busy. this bit is asserted when the terminal responds to the receive command with busy status, due to global busy bit set in rt 1553 status bits register, or command-specifc mkbusy bit set in the descriptor table control word. received data words were buffered normally. 8 ilcmd illegal command received. this bit is asserted when the illegalization table bit corresponding to the received com - mand is logic 1. the illegalization table should only contain nonzero values when illegal command detection is being applied. see section 19.2 for further information. 7 txrterr rt-rt transmit remote terminal error. this bit is set when the terminal decodes a valid rt-rt receive command, but one of four potential errors is detected in the second command word, cw2: (1) cw2 is addressed to broadcast address rt31. (2) the cw2 t/ r bit equals 0, (3) the cw2 subaddress is a mode command indicator, 00000 or 11111, or (4) cw2 has same non-broadcast terminal address as receive command word cw1. the txrterr bit is also set when status word received from the transmitting terminal is invalid (e.g., parity error) or bits 15:11 in the status word refect the wrong rt address (does not match cw2). 6 rtrt remote terminal to remote terminal transfer. assertion of this bit indicates the receive command was an error-free rt-to-rt transfer. 5 busid bus identifcation. if this bit equals zero, message was transacted on bus a. if bit equals one, it was trans - acted on bus b. 4-0 wc4:0 word count. this 5-bit feld contains the word count extracted from the command word. zero indicates 32 words. 20.1.2. transmit subaddress command the external host is responsible for organizing the data packet (i.e., storing n data words) in shared ram and initializ - ing the applicable data pointer. the host must allocate two memory locations at the starting address of the data record for device storage of the transmit subaddress message information word and time-tag word. here is an example data structure for a 3-word transmit command. notice that the data pointer points to the data structure starting address, not the frst data word. the data pointer is located in the transmit subaddress commands descriptor block. data buffer hex address word description word is written by ... data pointer equals 0x1500 0x1500 0x1501 0x1502 0x1503 0x1504 message information word time-tag word data word 1 data word 2 data word 3 device, after message completion host, prior to terminals data transmit HI-6130, hi-6131
holt integrated circuits 187 gaperr merr w3 w2 w1 w0 msb lsb 15 14 13 12 11 10 9876543210 w4 ilcmd x xx x wcterr busid rtrt wasbsy the following bits comprise the transmit subaddress message information word. bit no. mnemonic function 15,14 ----- not used. 13 gaperr gap error. assertion of this bit indicates bus activity was detected immediately after the transmit com - mand word, when a gap was expected. 12 wcterr word count error. this bit is asserted if command is received with unexpected data word(s). 11 ----- not used. 10 merr message error. this bit is asserted when message error status change occurs during command process - ing. see bits 12 and 13 for details. 9 wasbsy was busy status. this bit is asserted when the terminal responds to the transmit command with busy status, due to global busy bit set in rt 1553 status bits register, or command-specifc mkbusy bit set in the descriptor table control word. no data words were transmitted. 8 ilcmd illegal command received. this bit is asserted when the illegalization table bit corresponding to the received com - mand equals one. the illegalization table should only contain nonzero values when il - legal command detection is being applied. see section 19.2 for further information. 7 ----- not used. 6 rtrt remote terminal to remote terminal transfer. assertion of this bit indicates the transmit command was an error-free rt-to-rt transfer. 5 busid bus identifcation. if this bit equals zero, message was transacted on bus a. if bit equals one, it was trans - acted on bus b. 4-0 wc4:0 word count. this 5-bit feld contains the word count extracted from the command word. zero indicates 32 words. 20.2. mode command message information words mode command data structures in shared ram are similar to those for subaddresses. mode codes 0 through 15 (0x0f) do not have an associated data word, so data structures for these mode code values have just a message HI-6130, hi-6131
holt integrated circuits 188 information word and time-tag word. the message information word is stored at the memory address specifed by the descriptor table data pointer. mode codes 16 through 31 (0x10 through 0x1f) have one associated data word. the message information word is stored at the memory address specifed by the descriptor table data pointer, and the time-tag word is stored in the following location. the data word is stored at the memory address specifed by the data pointer plus two locations. 20.2.1. receive mode command the receive mode command data structure contains a message information word, a time-tag word and may con - tain one data word. if a receive mode command has a data word, the device may apply the data as defned by mil- std-1553, plus store the received single mode data word at the address specifed by the data pointer, plus two locations. refer to the mode code command summary in table 17 . here is an example data structure for a receive mode command with data (mode code values 0x10 through 0x1f). notice that the data pointer points to the data structure starting address, not the mode data word. the data pointer is located in the receive mode commands descriptor block, fully described later: data buffer hex address word description word is written by ... data pointer equals 0x1500 0x1500 0x1501 0x1502 message information word time-tag word mode data word device, after message completion three receive mode commands with data are not defned under mil-std-1553b. these are mc16, mc18 and mc19 (mode codes 0x10, 0x12 and 0x13 respectively). however the device responds in form if illegal command detection is not used (corresponding bits in illegalization table are logic 0) and the umcinv bit in the rt confguration register is logic 0. for mode code commands without data, the data structure contains only the message information word and time-tag word. here is an example data structure for a receive mode command without data (mode code values 0x00 through 0x0f). note: none of these receive mode commands are defned under mil-std-1553b but the device responds in form if illegal command detection is not used (corresponding bits in illegalization table are logic 0) and the umcinv bit in the rt confguration register is logic 0. notice that the data pointer points to the data structure starting address, the mes - sage information word. the data pointer is located in the receive mode commands descriptor block, fully described later: data buffer hex address word description word is written by ... data pointer equals 0x1500 0x1500 0x1501 message information word time-tag word device, after message completion synerr gaperr iwderr merr busid mc3 mc2 mc1 mc0 msb lsb 15 14 13 12 11 10 987654321 0 mc4 ilcmd wasbsy xx wcterr x the following bits comprise the receive mode message information word: HI-6130, hi-6131
holt integrated circuits 189 bit no. mnemonic function 15 ----- not used. 14 iwderr invalid word error. assertion of this bit indicates manchester error or parity error was observed in a received data word. 13 gaperr gap error. assertion of this bit indicates bus activity was detected immediately after a received mode data word or that a gap occurred before the data word was received. 12 wcterr word count error this bit is asserted if the command is received without expected mode data word, or with extra word. 11 synerr sync error. this bit is asserted when incorrect (command/status) sync type occurs in received mode data word. 10 merr message error. this bit is asserted when message error status change occurs during command process - ing. see bits 11- 14 for details. 9 wasbsy was busy status. this bit is asserted when the terminal responds to the mode command with busy status, due to global busy bit set in the rt 1553 status bits register, or command-specifc mk - busy bit set in the descriptor table control word. 8 ilcmd illegal command received. this bit is asserted when the illegalization table bit corresponding to the received com - mand equals one. the illegalization table should only contain nonzero values when il - legal command detection is being applied. see section 19.2 for further information. 7,6 ----- not used. 5 busid bus identifcation. if this bit equals zero, message was transacted on bus a. if bit equals one, it was trans - acted on bus b. 4-0 mc4:0 mode code. this 5-bit feld contains the mode code extracted from the command word. 20.2.2. transmit mode command the transmit mode command data structure contains a message information word, a time-tag word and may contain one data word. for mode commands with associated data word (mode codes 16-31 decimal) the host is responsible for loading the mode command data table before transmit mode commands are received (e.g., transmit vector word mode code). two mode codes have internally generated data words: mc18 transmit last command and mc19 transmit bit word. for these, the device automatically transmits the data word then copies the transmitted data value to the stored data structure. here is an example data structure for a transmit mode command with data (mode code values 0x10 through 0x1f). HI-6130, hi-6131
holt integrated circuits 190 this applies to mc16 transmit vector word. notice that the data pointer points to the data structure starting address, not the mode data word. the data pointer is located in the transmit mode commands descriptor block, fully described later: data buffer hex address word description word is written by ... data pointer equals 0x1500 0x1500 0x1501 0x1502 message information word time-tag word mode data word device, after message completion host, prior to terminals data transmit (except mc18, mc19 are written by the device after completion) three transmit mode commands with data are not defned under mil-std-1553b. these are mc17, mc20 and mc21 (mode codes 0x11, 0x14 and 0x15 respectively). however the device responds in form if illegal command detection is not used (corresponding bits in illegalization table are logic 0) and the umcinv bit in the rt confguration register is logic 0. for mode code commands without data, the data structure contains only the message information word and time-tag word. here is an example data structure for a transmit mode command without data (mode code values 0x00 through 0x0f). again, the data pointer points to the data structure starting address. the data pointer is located in the transmit mode commands descriptor block, fully described later: data buffer hex address word description word is written by ... data pointer equals 0x1500 0x1500 0x1501 message information word time-tag word device, after message completion gaperr merr busid mc3 mc2 mc1 mc0 msb lsb 15 14 13 12 11 10 9876543210 mc4 ilcmd xx xx wasbsy wcterr x the following bits comprise the mode transmit message information word: bit no. mnemonic function 15,14 ----- not used. 13 gaperr gap error. this bit is high when bus activity was detected immediately after the mode command word, when a gap was expected. 12 wcterr word count error this bit is asserted if command is received with unexpected data word(s). 11 ----- not used. 10 merr message error. this bit is asserted when message error status change occurs during command process - ing. see bits 12-13 for details. HI-6130, hi-6131
holt integrated circuits 191 bit no. mnemonic function 9 wasbsy was busy status. this bit is asserted when the terminal responds to the mode command with busy status, due to global busy bit set in rt 1553 status bits register, or command-specifc mk - busy bit set in the descriptor table control word. no mode data word was transmitted. 8 ilcmd illegal command received. this bit is asserted when the illegalization table bit corresponding to the received com - mand is logic 1. the illegalization table should only contain nonzero values when illegal command detection is being applied. see section 19.2 for further information. 7,6 ----- not used. 5 busid bus identifcation. if this bit equals zero, message was transacted on bus a. if bit equals one, it was trans - acted on bus b. 4-0 mc4:0 mode code. this 5-bit feld contains the mode code extracted from the command word. 20.3. ping-pong data buffering 20.3.1. double buffered (ping-pong) mode ping-pong buffer mode is a method for storing message and time-tag information and data associated with messages. each unique mil-std-1553 subaddress and mode code is assigned a pair of data buffers for transmit commands and a pair of data buffers for receive commands. the device retrieves buffer data for transmit commands, or stores buffer data for receive commands. during ping-pong operation, the device alternates message storage between data buffer a and data buffer b, on a message-by-message basis. when a subaddress or mode command uses ping-pong data buffer mode, its 4-word descriptor block in the descriptor table is defned as follows: descriptor word 1 control word descriptor word 2 data pointer a descriptor word 3 data pointer b descriptor word 4 broadcast data pointer if descriptor word 1 is stored at memory address n, descriptor word 2 is stored at address n+1, and the other two words are stored at addresses n+2 and n+3. prior to starting terminal operation, enable ping-pong buffering for any subaddress (or mode code) by asserting the ppen bit and negating the stopp bit in the descriptor control word. when the device detects ping-pong is selected (ppen = 1) and enabled (stopp = 0), it asserts the control word ppon bit to confrm ping-pong is active. during ping-pong operation, the rt determines the active data buffer at the beginning of message processing. the control word dpb bit indicates the data pointer to be used by the next command. dpb equals logic 0 means data pointer a is used next; dpb equals logic 1 means data pointer b is used next. for ping-pong, data pointers a and b HI-6130, hi-6131
holt integrated circuits 192 are static values pointing to the frst address in each buffer. at the conclusion of error-free message processing, the control word dpb bit is inverted so the next command ping-pongs to the other data buffer. each new message to the subaddress or mode code overwrites message data and information words written two messages back. the dpb bit does not toggle when a message ends in error, or if the command was illegal, or if busy status applied for the received command. in these cases, the next command will overwrite the same buffer. figure 18 is a general illustration of ping- pong buffer mode. figure 19 shows a specifc example. 20.3.2. ping-pong enable / disable handshake because ping-pong messages and host buffer servicing are asynchronous, there is potential for data collision. here is a data collision example: the host reads data from an earlier message while the device simultaneously writes new message data to the same buffer. the host reads a mix of new and old message data. collisions can occur for both transmit and receive messages. a handshake scheme lets the external host asynchronously service ping-pong data buffers without data collision. to off-load or load a subaddress (or mode code) buffer, the application software performs the following sequence: a. host asserts the control word stopp bit to suspend ping-pong operation for the subaddress. when the device recognizes stopp bit assertion, it negates the ppon bit to acknowledge ping-pong is disabled. while ppon remains low, the last written (or read) data buffer is protected against device updates. during this time, new messages use the active buffer indicated by the control word dpa bit. recurring messages repeatedly use the same buffer until ping-pong resumes. b. host services the last-used data buffer. if the control word dpb bit equals logic 1, the last command used buffer a. the host application software off-loads or loads inactive buffer a while the remote terminal uses active buffer b for new message(s). if the dpb bit equals logic 0, the last command used buffer b. the host application software off-loads or loads inactive buffer b while the remote terminal uses active buffer a for any new messages. each new receive message overwrites buffer contents from the last receive message. to avoid possible data loss, host buffer servicing should be timed for completion before a second message can occur. c. host negates the control word stopp bit to resume ping-pong operation for the subaddress. when the rt recognizes the stopp bit is reset, it sets the ppon bit to acknowledge ping-pong is again active. as long as ppon remains set, the device alternates between data buffers a and b for new messages. HI-6130, hi-6131
holt integrated circuits 193 message processing alternates between data buffers a and b. upon sucessful message completion, the dpb bit in descriptor control word is updated so next message uses other buffer. buffers are overwritten every other message. separate buffer for broadcast messages is optional. there is no alternate buffer for successive broadcast messages. b?cast data pointer data pointer a data pointer b control word descriptor block for subaddress memory address for the applicable subaddress block is derived from the decoded command word subaddress buffer space for broadcast (optional) broadcast message (if notice2 is asserted) increasing memory address assigned subaddress data buffer b data word 1 message info word time-tag word data words 2-31 data word 32 message #2 message #4 message #6 etc. data word 1 message info word time-tag word data words 2-31 data word 32 message #1 message #3 message #5 etc. assigned subaddress data buffer b data word 1 message info word time-tag word data words 2-31 data word 32 figure 18. illustration of ping-pong buffer mode HI-6130, hi-6131
holt integrated circuits 194 20.3.3. broadcast message handling in ping-pong mode for mil-std-1553b notice ii compliance, a remote terminal should be capable of storing data from broadcast mes - sages separately from non-broadcast message data. some applications may not include this requirement. the stan - dard does not stipulate where data separation should occur (e.g., within the rt or within the external host) so the device provides alternative strategies. when the notice2 bit in the rt confguration register is 1 and the bcstinv bit is 0, ping-pong mode subaddresses (or mode codes) will buffer data words from broadcast and non-broadcast messages separately. broadcast message information and data are stored in the broadcast data buffer; non-broadcast message information and data are stored in ping-pong buffers a and b. since there is just one broadcast data buffer, the notice2 option treats broadcast messages as exceptions to normal ping-pong mode. when using the notice2 option, broadcast data buffer servicing should have high priority, because a closely following broadcast message will overwrite the broadcast buffer. every mode command and subaddress (including transmit subaddresses) must have an assigned valid broad - cast data pointer when notice2 is asserted. when the notice2 bit in the rt confguration register is 1 and the bcstinv bit is 0, reception of a broadcast-transmit message updates the message information and time-tag words for the assigned broadcast buffer, but no data is transmitted on the bus. since broadcast-transmit is not allowed, multiple transmit subaddresses may share a common bit bucket broadcast buffer. a two word buffer is suffcient for storing the miw and time-tag word. when using ping-pong mode, there are two ways to handle broadcast messages, when broadcast is enabled: option 1 for ping-pong mode broadcast messages: this option isolates broadcast message information in the broadcast data buffer. if the descriptor control word ibr bit and interrupt enable register ibr bit are both set, reception of broadcast messages generates an int host interrupt. to prevent data loss, the broadcast data buffer must be serviced before the next broadcast message occurs. broadcast messages do not affect non-broadcast message ping-pong; the control word dpb bit does not toggle after broadcast message completion. option 1 setup: at initialization, host asserts the notice2 bit in the rt confguration register and sets the ibr (interrupt broadcast received) bit in descriptor control word(s). the ibr bit is asserted in the interrupt enable register. when a broadcast command is received, message information and data is stored in the broadcast data buffer and an int interrupt is generated. the host must read the interrupt log to determine the originating subaddress (or mode code), then service the broadcast data buffer for that subaddress (or mode code) before another broadcast message to the same subaddress (or mode code) arrives. option 2 for ping-pong mode broadcast messages: the second alternative stores both broadcast and non-broadcast message information in the ping-pong data buffers a and b. iwa interrupts can signal arrival of any new message. the rt handles broadcast messages just like non- broadcast messages, except the message information word bcast bit is asserted to identify broadcast messages during host buffer servicing. all messages toggle the control word dpb bit in message post-processing. for notice ii compliance, separation of broadcast and non-broadcast data occurs within the host. option 2 setup: at initialization, host negates the notice2 bit in the rt confguration register. if iwa interrupts are used, the host asserts the descriptor control word iwa (interrupt when accessed) bit 14 and the corresponding bit is asserted in the interrupt enable register. using this option, the ibr interrupt is probably not used. the host typically services the ping-pong data buffers a and b whenever a message is transacted. using the setup above, this occurs whenever the subaddress iwa interrupt generates an int interrupt output for the host. the host must read the interrupt log to determine the originating subaddress or mode code. the applicable data buffer is indicated by the dpb bit in the receive control word. the message information word bcast bit is asserted if the message was broadcast. HI-6130, hi-6131
holt integrated circuits 195 b?cast data pointer data pointer b data pointer a control word increasing memory address control word = 0x2010 ping-pong mode, ibr interrupt initialized descriptor values 0x1500 0x1501 0x1502 0x1503 - 0x1520 0x1521 0x1522 0x1523 0x1524 0x1525 - 0x1542 0x1543 0x1544 0x1545 0x1546 0x1547 - 0x1564 0x1565 ram address device sets control word bcast bit (dpb bit remains static) ibr interrupt is generated device resets control word dpb and bcast bits data word 1 msg info word bc time-tag word bc data words 2-31 data word 32 data word 1 msg info word b time-tag word b data words 2-31 data word 32 data word 1 msg info word a time-tag word a data words 2-31 data word 32 receive message #2 broadcast, 32 data words receive message #3 non-broadcast, 32 data words device resets control word dpb bit receive message #1 non-broadcast, 32 data words message #4 also uses this buffer, if not broadcast broadcast data pointer = 0x1544 start address in ram data pointer b = 0x1522 buffer b start address in ram data pointer a = 0x1500 buffer a start address in ram descriptor block for a receive subaddress assigned subaddress broadcast data buffer assigned subaddress data buffer b assigned subaddress data buffer a following reset (which resets control word dpb bit), the subaddress transacts 4 commands of 32 data words each. the notice 2 option is enabled so the device segregates data from broadcast and non-broadcast messages. message #2 is a broadcast command, while the other three messages are non-broadcast. notice that the broadcast message does not affect dpb bit, but the following message resets bcast bit. the interspersed broadcast command does not affect alternation between buffer a and buffer b. figure 19. ping-pong buffer mode example for a receive subaddress HI-6130, hi-6131
holt integrated circuits 196 20.4. indexed data buffer mode also called single buffer mode, indexed buffering is one method for storing message and time-tag information and data associated with messages. buffer mode is selected for each subaddress or mode code in the descriptor table control words. indexed mode is enabled when control word ppen, cir1en and cir2en bits are all zero. when a subaddress or mode command uses the indexed data buffer mode, its 4-word descriptor block in the descrip - tor table is defned as follows: descriptor word 1 control word descriptor word 2 data pointer a descriptor word 3 indx index word descriptor word 4 broadcast data pointer if descriptor word 1 is stored at memory address n, descriptor word 2 is stored at address n+1, and the other two words are stored at addresses n+2 and n+3. as the name implies, all message information and data is stored in a single buffer, indexed by descriptor word data pointer a. the descriptor control word dpb bit is dont care. the host initializes the desired message count in de - scriptor indx word. during message processing, the device retrieves or stores data words from the address specifed by descriptor data pointer a, automatically incrementing the pointer address as words are read or stored. data pointer a is updated during command post-processing with the current buffer address unless the message index count in de - scriptor indx (word 3 of descriptor block) decrements to zero upon completion of the message. figure 20 is a general illustration of indexed single buffer mode. figure 21 shows a specifc example. to set up a terminal subaddress to buffer multiple messages, the host writes the desired index count (indx) to subad - dress descriptor word 3. the initial indx value ranges from zero to 3ff hex (1023) messages. the device decrements the indx count each time an error-free message is transacted, and the data pointer is updated to the frst memory address to be used for the next message. if indx decrements from one to zero and control word ixeqz bit 15 is as - serted, the ixeqz bit is set in the interrupt pending register. if the corresponding bit in the interrupt enable register is asserted, an int interrupt is generated when indx decrements from one to zero. indx counter decrement does not occur if the command was illegalized or if indx already equals zero. once indx equals zero, further commands will overwrite the last-written data buffer block and the data pointer value is not up - dated after successful message completion. when using index mode with a non-zero indx value, the host must remember the initial data pointer a address. the data pointer a word is not automatically reinitialized to the buffer start address when indx decrements from 1 to 0. 20.4.1. single message mode when index mode is initialized with an indx value of zero, the subaddress or mode code is operating in single message mode. here, the same data block is repeatedly over-read (for transmit data) or overwritten (for receive or broadcast data). the dpa pointer is not updated at the end of each message. the chief advantage of single message mode is simplicity. in comparison to other data buffering options, the single message buffer uses an absolute minimum amount of memory space. the ixeqz interrupt cannot be used for this scheme (indx is always zero) but iwa inter - rupts may be used. single message mode is best suited to synchronous data transfer where the host processor can reliably read or write new message data prior to the start of the next message to the same subaddress or mode code. 20.4.2. broadcast message handling in index mode for mil-std-1553b notice ii compliance, a remote terminal should be capable of storing data from broadcast mes - sages separately from non-broadcast message data. some applications may not include this requirement. the stan - dard does not stipulate where data separation should occur (e.g., within the rt or within the external host) so the device supports alternative strategies. HI-6130, hi-6131
holt integrated circuits 197 when the notice2 bit is logic 1 in the rt confguration register, broadcast message data is stored in a broadcast data buffer assigned for the subaddress or mode command. each subaddress or mode command must have an as - signed, valid non-zero broadcast buffer address. non-broadcast message data is stored in data buffer a. there are two ways to deal with broadcast messages in indexed buffer mode: option 1 for index mode broadcast messages: the frst alternative isolates broadcast message information in the broadcast data buffer. if the descriptor control word ibr bit and interrupt enable register ibr bit are both set, reception of broadcast messages generates an int interrupt to the host. the broadcast data buffer must be processed before another broadcast message arrives to prevent loss of data. broadcast messages do not decrement the indx register, and data pointer a is not updated in message post- processing. this scheme may be well suited for single message mode (indx = 0) when the host can reliably service either the broadcast data buffer or data buffer a before the next receive message arrives for the same subaddress (or mode code). option 1 setup: at initialization, host asserts notice2 bit in the rt confguration register and sets the control word ibr (interrupt broadcast received) bit for each index mode descriptor block. the ibr bit is also asserted in the inter - rupt enable register. when a broadcast command is received, message information and data are stored in the broadcast data buffer. if descriptor control word ibr bit is set, an int interrupt is generated. the host must read the interrupt log to determine the originating subaddress (or mode code) then service the broadcast data buffer for that subaddress (or mode code) before the next broadcast message to the same subaddress (or mode code) arrives. option 2 for index mode broadcast messages: the second alternative stores both broadcast and non-broadcast message information in data buffer a. optional ibr interrupts can signal arrival of broadcast messages. the rt handles broadcast messages just like non-broadcast messages, except the message information word bcast bit is asserted to identify broadcast messages during host buffer servicing. all messages decrement the indx register and data pointer a is updated in message post-process - ing. this scheme is compatible with single message mode or conventional n-message indexing. for notice ii compli - ance, separation of broadcast and non-broadcast data occurs within the host. option 2 setup: at initialization, host negates the notice2 bit in the rt confguration register. if broadcast interrupts are used, the control word ibr (interrupt broadcast received) bit is asserted at each desired index mode descriptor block. the ibr bit is also asserted in the interrupt enable register. using option 2, the host has several options for servicing data buffer a: (a) when indx decrements from one to zero (using the ixeqz interrupt), (b) when a broadcast message occurs (using the ibr interrupt) or (c) when any message arrives (using the iwa interrupt). HI-6130, hi-6131
holt integrated circuits 198 b?cast data pointer data pointer a indx index count control word next message data word 1 message info word time-tag word data word(s) data word n data word 1 message info word time-tag word data word(s) data word n data word 1 message info word time-tag word data word(s) data word n data word 1 message info word time-tag word data word(s) data word n descriptor block for subaddress assigned subaddress buffer space increasing memory address memory address for the applicable subaddress block is derived from the decoded command word subaddress buffer space for broadcast (optional) broadcast message (if notice2 is asserted) current message preceding message upon successful message completion, if non-zero the indx count in descriptor word 3 is decremented. if decremented result is non-zero, data pointer a is adjusted so next message is stored above just-completed message. if decremented indx is zero, data pointer a remains static and ixeqz interrupt occurs if enabled in control word. figure 20. illustration of indexed buffer mode HI-6130, hi-6131
holt integrated circuits 199 0x1500 0x1501 0x1502 0x1503 0x1504 0x1505 0x1506 0x1507 0x1508 0x1509 0x150a ram address messages #2, #3, etc receive 4 words broadcast data pointer = 0xxxxx don?t care index = 0x0002 initialize index for 2 messages data pointer a = 0x1500 buffer start address in ram control word = 0x8000 index mode, ixeqz interrupt initialized descriptor values index equals two index decrements to one data pointer a = 0x1505 for message #2, index decrements to zero. data pointer a = 0x1505 (static) ixeqz interrupt is generated for message #3 and beyond, the data buffer is overwritten. index remains zero (static) data pointer a = 0x1505 (static) and no ixeqz interrupt occurs. data word 1 msg info word 1 time-tag word 1 data word 2 data word 3 data word 1 msg info word 1 time-tag word 1 data word 2 data word 3 data word 4 assigned receive subaddress buffer increasing memory address messages #1 receive 3 words b?cast data pointer data pointer a indx index count control word descriptor block for a receive subaddress figure 21. indexed buffer mode example for a receive subaddress (broadcast disabled) HI-6130, hi-6131
holt integrated circuits 200 20.5. circular buffer mode 1 the device offers two circular data buffer modes as alternatives to ping-pong and indexed buffering. these circular buffer options only apply for subaddress commands, not mode code commands. circular buffering simplifes software servicing of the remote terminal when implementing bulk data transfers. a circular buffer mode can be selected for any subaddress by properly initializing its descriptor control word. circular buffer mode 1 is selected when descriptor control word ppen and cir2en bits are both 0, and the cir1en bit is logic 1. when a subaddress uses circular buffer mode 1, its four word block in the descriptor table is defned as follows: descriptor word 1 control word descriptor word 2 sa (buffer start address) descriptor word 3 ca (buffer current address) descriptor word 4 ea (buffer end address) if descriptor word 1 is stored at memory address n, descriptor word 2 is stored at address n+1, and the other two words are stored at addresses n+2 and n+3. figure 22 provides a generalized illustration of circular buffer mode 1, while figure 23 shows a specifc example. circular buffer mode 1 uses a single user-defned buffer that merges all transmit or receive data, along with message information. two words (message information and time-tag) are stored at the beginning of the block for each mes - sage, followed by the message data word(s). the mode 1 buffer pointers roll over (are reset to their base addresses) when the allocated data buffer memory is full. for each valid receive message, the device enters a message information word, time-tag word and data word(s) into the circular receive buffer. for each valid transmit message, the device enters a message information word and a time-tag word into reserved memory locations within the circular transmit buffer. the device automatically controls the wrap around of circular buffers. two pointers defne circular buffer length: start of buffer (lowest address) and end of buffer (highest address). user specifes the start of buffer (sa) by writing the lowest address value into the second word of a unique subaddress descriptor block. the user defnes the bottom of the buffer (ea) by writing the highest address value to the fourth word of that unique descriptor block. both sa and ea remain static during message processing. the third word in the descriptor block identifes the current address ca (i.e., last accessed address plus one). the circular buffer wraps to the start address after completing a message that results in ca being greater than or equal to ea. if ca increments past ea during message processing, the device will access memory addresses greater than the ea value. reserve 33 address locations past the ea address to accommodate a worst-case 32 data word message with a record starting at address = ea minus 1. each receive subaddress and transmit subaddress may have a unique circular buffer assignment. the rt decodes the command word t/ r bit, subaddress feld and word count / mode code feld to select the unique command descriptor block containing the control word, sa pointer, ca pointer and ea pointer. for receive messages, the device stores the message information word to the address specifed by ca, the time-tag word into ca+1 and the data into the next n locations starting with ca+2. for transmit messages, the device stores the message information word to the address specifed by ca and the time-tag word into ca+1. retrieval of data for transmission starts at address ca+2. when entering multiple transmit command data packets into the circular buffer, delimit each data packet with two reserved memory locations. the device stores the message information word and time-tag word into the reserved locations when processing the command. message processing for all commands begins with the device reading the unique descriptor block for the subaddress or mode code specifed by the t/ r bit, subaddress and word count felds in the received command word. for receive messages, the device stores n received data words in the circular data buffer. the frst data word re - ceived is stored at the location specifed by the ca pointer +2. after message completion, the device stores the mes - sage information word and time-tag words to addresses ca and ca+1 respectively. if no errors were detected, the HI-6130, hi-6131
holt integrated circuits 201 device updates descriptor ca register. if the next address location (last stored data word +1) is less than or equal to ea, ca is updated to (last stored address +1). if the next address location (last stored data word +1) is greater than ea, the data buffer is full (or empty); ca is updated to the sa value. if descriptor control word ixeqz bit is asserted (and if interrupt enable register ixeqz bit is asserted) the device generates an interrupt to indicate full receive buffer by asserting the int interrupt output. although all messages store message information and time-tag words, no data is stored if the message ended with error, or if the busy status bit was set or if the commend was illegal (example: illegalized word count). such messages do not update ca, so the next message overwrites the same buffer space. for transmit commands, the device begins transmission of data retrieving the frst data word stored at address ca+2. (reminder: addresses ca and ca+1 are reserved for the message information and time-tag words.) when message processing is complete, the device writes the message information and time-tag words into the buffer. if no errors were detected, the device updates descriptor ca register. if the next address location (last retrieved data word +1) is less than or equal to ea, ca is updated to (last retrieved address +1). if the next address location (last retrieved data word +1) is greater than ea, the transmit data buffer is empty; ca is updated to the sa value. if the descriptor control word ixeqz bit is asserted (and if the interrupt enable register ixeqz bit is asserted) the device indicates transmit buffer empty by asserting the int interrupt output. circular buffer mode 1 does not support notice2 segregation of broadcast data, even when the notice2 bit equals 1 in the rt confguration register. data from broadcast and non-broadcast receive commands is stored in the same buffer. the bcast bit in the message information word refects broadcast or non-broadcast status for each stored message. if broadcast messages are not expected during data block transmission, the host can illegalize broadcast commands for the subaddress. broadcast illegalization can be done either permanently, or only when data block transmission is scheduled. for transmit subaddresses using circular buffer mode 1, occurrences of broadcast-transmit commands to rt31 do not result in bus transmission. however these messages update the message information word addressed by the current address (ca) pointer (and following time-tag word) but afterwards, the ca pointer remains unchanged. the next transmit command to the same subaddress, whether broadcast or not, overwrites the message information and time-tag word locations written by the previous broadcast transmit command. HI-6130, hi-6131
holt integrated circuits 202 end address start address current address control word current message last message in data block end address current address start address data word 1 message info word time-tag word data word(s) data word n data word 1 message info word time-tag word data word(s) data word n more messages in data block more messages in data block data word 1 message info word time-tag word data word(s) data word n firstmessage in data block descriptor block for subaddress memory address for the applicable subaddress block is derived from the decoded command word assigned subaddress circular buffer increasing memory address descriptor block is initialized so current address equals buffer start address. after each successful message transaction, current address is adjusted to point past last data word accessed. if adjusted current address points past end address, the current address is reinitialized to match start address and an optional interrupt is generated to notify host that the pre-determined data block was fully transacted. figure 22. illustration of circular buffer mode 1 HI-6130, hi-6131
holt integrated circuits 203 contro lw ord increasing memory address 0x1500 0x1501 0x1502 0x1503 - 0x1520 0x1521 0x1522 0x1523 0x1524 0x1525 - 0x1542 0x1543 0x1544 0x1545 0x1546 0x1547 - 0x1564 0x1565 ram address unless serviced by host after message #3 interrupt, message #4 will overwrite buffer, starting at 0x1500 buffer end address (1 + data word 32 address) end address. device updates current address to equal the start address, 0x1500. ixeqz interrupt is generated. receive message #3 32 data words end address start address current address (1 + data word 32 address) < end address. device updates current address to 0x1544. data word 1 msg info word 3 time-tag word 3 data words 2-31 data word 32 data word 1 msg info word 2 time-tag word 2 data words 2-31 data word 32 data word 1 msg info word 1 time-tag word 1 data words 2-31 data word 32 buffer start address receive message #3 32 data words receive message #3 32 data words (1 + data word 32 address) < end address. device updates current address to 0x1522. descriptor block for a receive subaddress control word = 0x8001 circular mode 1, ixeqz interrupt initialized descriptor values start address = 0x1500 buffer start address in ram current address = 0x1500 buffer current address in ram end address = 0x1545 buffer end address in ram unlike indexed mode, data block completion is based on buffer full / buffer empty, not number of messages. buffer size was purposely sized to yield remaining capacity after 2 full-count messages, to illustrate device behavior. the circular buffer should have a 33-word pad beyond its end address to deal with buffer overrun without data loss. figure 23. circular buffer mode 1 example for a receive subaddress HI-6130, hi-6131
holt integrated circuits 204 20.6. circular buffer mode 2 circular buffer mode 2 segregates message data and message information in separate host-defned buffers. separat - ing data from message information simplifes the host software that loads or unloads the data to or from the buffer. after a predetermined number of messages has been transacted, buffer address pointers for data and message information are automatically reset to their base addresses. figure 24 is a generalized illustration of circular buffer mode 2, while figure 25 shows a specifc example. circular buffer mode 2 is selected when the control word ppen bit is zero and the cir2en bit is logic 1. when the cir2en bit is high, the cir1en bit is dont care. the descriptor control word dpb bit is not used. any receive subaddress using circular buffer mode 2 has two circular buffers: a data storage buffer and a message information buffer. a separate buffer pair may be used for transmit commands to the same subaddress, if it also uses circular buffer mode 2. each transmit and receive subaddress using circular buffer mode 2 may have unique data buf - fer and message info buffer assignments. careful management (involving the bus controller) may allow buffer sharing, as long as multiple message sequences to a given subaddress are not interrupted by messages to other subaddresses that use the same buffer space. when a subaddress uses circular buffer mode 2, its descriptor table 4-word block is defned as follows: descriptor word 1 control word descriptor word 2 sa (buffer start address) descriptor word 3 ca (buffer current address) descriptor word 4 miba (message info buffer addr) if descriptor word 1 is stored at memory address n, descriptor word 2 is stored at address n+1, and the other two words are stored at addresses n+2 and n+3. the frst word in the descriptor block is the control word. the second and third words in the descriptor are the start address (sa) and current address (ca) pointers. the message informa - tion buffer address (miba) points to the storage location for the message information word from the next occurring message. each time a message is completed, the device writes a new message information word and time-tag word in the mib (message information buffer) at the miba address and following location, respectively. the miba pointer is not updated if message error occurred, if the busy status bit was set, or if the command was illegalized (for example an illegal word count expressed in the command word.) for these situations, the message information and time-tag words are still written, but mib updates for the following message will overwrite the just-written message information and time-tag word addresses. for error-free receive messages, received data words are stored in the data buffer after message completion, starting at the ca address value. the ca value is then updated for next-message readiness. after writing the two mib words, the device updates the miba value to show the buffer address to be used by the next message. until the predetermined number of error-free messages is transacted, the miba value is double-incremented at each update. before updating the miba in descriptor word 4, the pre-existing miba value is incremented once then checked for full count, occurring when all n low-order address bits initialized to zero (explained below) become n one bits. full count means the predetermined number of successful messages was completed. when this occurs, the ca and mib pointers are automatically written to their initialized values by the device. to preserve data integrity, the trxdb bit should be set in the rt confguration register to avoid storing incomplete data from messages resulting in error. with trxdb asserted, the host is not bothered by message retries caused by errors. the buffer empty/full interrupt (if enabled) is generated only upon successful transaction of the entire n- message data block. to initialize circular buffer mode 2, the host must know the number of messages to be transacted, always a power of two: 1, 2, 4, 8, 16, 32, 64, 128, 256 or 512 messages. the host writes descriptor control word bits 7:4 with an encoded 4-bit value to set the fxed number of messages to be transacted. this is illustrated in table 16 . the host initializes the HI-6130, hi-6131
holt integrated circuits 205 descriptor block miba pointer with a message information buffer starting address. because the mib stores two words for each message, the allocated mib space should equal 2x the number of messages. the initially-loaded mib base address value is restricted. some lower bits of the starting address must be zero so the device can restore the miba pointer to the initial mib base address after the predetermined message count is transact - ed. as illustrated in table 16 , the required number of logic-0 bits depends on the message count. initializing the miba base address with more trailing zeros than indicated is acceptable; initializing less trailing zeros will cause malfunction. allocated space in the data buffer (see column 3, table 16 ) assumes each message has the maximum 32 data words. if messages contain less than 32 words, the data buffer size can be reduced. since circular buffer mode 2 counts messages, values in all remaining table 16 columns remain valid when message word count is reduced. the host may read the miba value to determine the number of messages that have occurred since initialization. by reading the initially-zeroed lower bits of the mib address, the host may determine the number of the next occurring message. from table 16 , a block of 128 messages requires 8 trailing zeros in the initial miba address, for example, 0x0f00. after each message is completed, the miba value is updated (0x0f02, 0x0f04, etc.) the device detects message block completion when all required initially-zero trailing address bits equal 1 after miba is incremented once. in our example, miba would increment from 0x0ffe to 0x0fff. when full count occurs, the device updates miba to the original value (e.g., 0x0f00) and copies the sa starting address value to ca current address register, ready for buffer service by the host. the device optionally generates a buffer empty-full interrupt for the host when block transfer is completed. during block transfer, the host can read the miba value to determine the number of additional messages needed be - fore the n-message data block is complete. message processing for all commands begins with the rt reading the unique descriptor block for the subaddress specifed by the t/ r bit, subaddress and word count felds in the received command word. table 16. circular buffer mode 2 (initialization factors based on message block size) number of messages control word bits 7:4 cir2zn field required data space if 32 words / msg required mib space, 2 words / msg initial miba value, showing the required leading and trailing zeros 2 0010 (2) 64 4 0xxxxxxxxxxxx00 4 0011 (3) 128 8 0xxxxxxxxxxx000 8 0100 (4) 256 16 0xxxxxxxxxx0000 16 0101 (5) 512 32 0xxxxxxxxx00000 32 0110 (6) 1,024 64 0xxxxxxxx000000 64 0111 (7) 2,048 128 0xxxxxxx0000000 128 1000 (8) 4,096 256 0xxxxxx00000000 256 1001 (9) 8,192 512 0xxxxx000000000 512 1010 (a) 16,384 1,024 0xxxx0000000000 HI-6130, hi-6131
holt integrated circuits 206 for receive subaddresses using circular buffer mode 2, the device stores received data words in the circular data buffer. the frst data word received for each message is stored at the location indicated by the ca pointer. after the correct number of words is received (as specifed in the command word) the device writes message information and time-tag words in the message information buffer then updates the descriptor ca current address and miba message information pointers for next-message readiness. if the predetermined total number of messages has not yet been transacted, miba points to the next location in the message information buffer and ca points to the next location in the data buffer. if the completed message is the last message in the block, the ca current (data) address and miba message information pointers are reinitialized to their base address values. (control word bits 7:4 tell the device how many miba lower bits to reset.) if the descriptor control word ixeqz bit is asserted (and if the interrupt enable register ixeqz bit is asserted) the device generates a buffer full / empty interrupt, asserting the int interrupt output. for transmit subaddresses using circular buffer mode 2, the device transmits data from the assigned ram buffer, starting at the location specifed by the ca pointer. the frst data word transmitted is stored at the location specifed by the ca pointer. after all data words are transmitted (as specifed in the command word) the device writes message information and time-tag words in the message information buffer then updates the descriptor ca current address and miba message information pointers for next-message readiness. if the predetermined total number of messages has not yet been transacted, miba points to the next location in the message information buffer and ca points to the next location in the data buffer. if the completed message is the last message in the block, the ca current (data) ad - dress and miba message information pointers are reinitialized to their base address values. (control word bits 7:4 tell the device how many miba lower bits to reset.) if the descriptor control word ixeqz bit is asserted (and if the interrupt enable register ixeqz bit is asserted) the device generates a buffer full / empty interrupt, asserting the int interrupt output. circular buffer mode 2 does not support notice2 segregation of broadcast data, even when the notice2 bit equals 1 in the rt confguration register. data words from broadcast receive commands are stored in the same buffer with data from non-broadcast receive commands. the bcast bit in the message information word refects broadcast or non-broadcast status for each stored message. if broadcast messages to the subaddresss are not expected during data block transmission or will result in data block error, the host can illegalize broadcast commands for the subad - dress, either permanently or only when block transmission is scheduled. for transmit subaddresses using circular buffer mode 2, occurrences of broadcast-transmit commands to rt31 do not result in bus transmission. however these messages update the message information word addressed by the message information block (mib) pointer (and the following time-tag word) but afterwards, the mib and ca pointers remain unchanged. the next transmit command to the same subaddress, whether broadcast or not, overwrites the message information and time-tag word locations written by the previous broadcast transmit command. HI-6130, hi-6131
holt integrated circuits 207 mib address start address current address control word data word 1 message info word time-tag word data word(s) data word n message info word time-tag word message info word time-tag word data word 1 data word(s) data word n data word 1 data word(s) data word n current address start address assigned subaddress circular data buffer current message last message in data block firstmessage in data block descriptor block for subaddress increasing memory address current message last message in data block firstmessage in data block memory address for the applicable subaddress block is derived from the decoded command word assigned subaddress message info buffer (mib) segregated storage for data and message information simplifies host loading / offloading of buffered data. descriptor mib address tracks number of messages. full count occurs when n initialized 0-bits become n 1-bits. when full number of messages in block is transacted, an optional interrupt is generated to notify host. figure 24. illustration of circular buffer mode 2 HI-6130, hi-6131
holt integrated circuits 208 control word 0x1500 0x1501 - 0x151e 0x151f 0x1520 0x1521 - 0x153e 0x153f 0x1540 0x1541 - 0x155e 0x155f msg count increments to 1. device updates ca to 0x1520 and updates miba to 0x1602. mib address start address current address data word buffer msg count increments to 2. device updates ca to 0x1540 and updates miba to 0x1604. 0x1560 0x1561 - 0x157e 0x157f msg count increments to 3. device updates ca to 0x1560 and updates miba to 0x1606. msg count increments to 4, full count, data block complete. device updates ca to equal buffer start address 0x1500. device updates miba to equal mib start address 0x1600. ixeqz interrupt is generated. message information buffer (mib) ram address 0x1600 0x1601 0x1602 0x1603 0x1604 0x1605 0x1606 0x1607 data word 1 data words 2-31 data word 32 data word 1 data words 2-31 data word 32 data word 1 data words 2-31 data word 32 data word 1 data words 2-31 data word 32 msg info word 3 time-tag word 3 msg info word 2 time-tag word 2 msg info word 1 time-tag word 1 msg info word 4 time-tag word 4 ram address increasing memory address descriptor block for a receive subaddress control word = 0x8042 circular mode 2, 4 messages, ixeqz interrupt initialized descriptor values start address = 0x1500 buffer start address in ram current address = 0x1500 buffer current address in ram mib address = 0x1600 mib start address in ram receive message #3 32 data words receive message #4 32 data words receive message #2 32 data words receive message #1 32 data words data block completion is based on number of messages, not buffer full or buffer empty. example is set to successfully transact four 32 data word receive messages, then generate ixeqz interrupt for host. the data buffer requires minimal processing by host because message information words are stored separately in mib. figure 25. circular buffer mode 2 example for a receive subaddress HI-6130, hi-6131
holt integrated circuits 209 21. remote terminal rt1 and rt2 mode command processing 21.1. general considerations the device provides decoding for all mode code combinations, consistent with mil-std-1553b requirements. several mode command options are provided to suit any application requirement: in the rt confguration register, the option bit umcinv (undefned mode codes invalid) globally defnes whether un - defned mode code commands are treated as valid (default) or invalid commands. this bit applies only to the following 22 mode code commands that are undefned in mil-std-1553b: mode codes 0 through 15 with t/ r bit = 0 mode codes16, 18 and19 witht/ r bit = 0 mode codes 17, 20 and 21 with t/ r bit = 1 if the umcinv bit is low (default after mr reset) undefned mode code commands are considered valid and rt re - sponse is based on individual mode command settings in the illegalization table: if the commands table bit equals 0, the mode command is legal; the rt responds in form and updates status. if the commands table bit equals 1 the mode command is illegal, the rt asserts message error status and (if non-broadcast) transmits only its status word without associated data word. table 17 describes explicit terminal response for each mode code value and command t/ r bit state, based on various option settings. if umcinv is asserted, the 22 undefned mode code commands are treated as invalid: there is no terminal recognition of the command. no command response occurs and status remains unchanged for the beneft of following transmit status or transmit last command mode commands. if umcinv is low, the device determines legal vs. illegal status of commands from the illegalization table. if the termi - nal does not use illegal command detection, the illegalization table should be left in its post-reset default state, all val - ues equal logic 0. in this case, the terminal provides in form response to all valid commands. the terminal responds with clear status and a transmitted mode data word for mode commands 16-31 with t/ r bit equals 1. assigned data buffer locations can be initialized to provide predictable in form responses for all transmit mode codes 16-31. (if um - cinv is asserted, the terminal will not respond or update status for received mode codes 17, 20 and 21 with t/ r = 1.) to use illegal command detection, the host modifes the illegalization table to make illegal any combination subad - dress and mode code commands. this may include undefned mode codes, reserved mode codes, and/or mode codes not implemented in the application. note: mode command mc0 dynamic bus control cannot be implemented in the device since the HI-6130/31 cannot act as a bus controller. therefore, the dynamic bus control acceptance status bit cannot be set in the outgoing status word from this device. 21.2. mode command interrupts for mode commands, interrupt generation is programmed by the top three bits in the descriptor table control word. notice that broadcast-transmit interrupts can be enabled for mode code values in the range of 0 - 15, but broadcast- transmit mode codes 16 - 31 are not allowed. when a mode command is received and the iwa interrupt bit is asserted in its descriptor control word, that command will generate a host interrupt if the iwa bit is high in the interrupt enable register. the iwa bit is asserted in the pending interrupt register and the int interrupt output is asserted. before int interrupt assertion, the device updates the interrupt log buffer, writing a new iiw interrupt information word and a new iaw interrupt address word. the iwa (interrupt when accessed) bit is asserted in the new iiw to indicate interrupt type. the iaw contains the descriptor table address for the mode commands control word, based on mode code value and command word t/ r bit state. the host reads the iaw to determine the command that caused the interrupt. HI-6130, hi-6131
holt integrated circuits 210 21.3. mode command data words mode commands having mode code values from 0 through 15 (decimal) do not have an associated data word. these are received as command word only, never having a contiguous data word. the terminal response to valid mode com - mands 0-15 always consists of status word only, assuming command was not broadcast. mode commands having mode code values from 16 through 31 (decimal) always have an associated data word. when the command word t/ r bit equals 0, the terminal receives a data word, contiguously following the command word. when valid legal mode commands 16-31 arrive with t/ r bit equal to 1, the terminal responds by transmitting its status word with a single data word. when the smcp option bit in the rt confguration register is zero, individual data words for mode codes 16-31 deci - mal are stored in an indexed or ping-pong buffer assigned by the mode commands descriptor table entry. circular buffer methods are not available for mode code commands. when the smcp option bit in the rt confguration register is asserted, individual data words for mode codes 16-31 decimal are stored within the descriptor table itself. this is explained next. table 17. mode code command summary command t/ r bit mode code mil-std-1553 defned function associated data word broadcast allowed see note binary dec. 0 00000 to 01111 0 to 15 undefned mode commands 0 - 15 when t/ r bit = 0 no no (1) 1 00000 0 dynamic bus control no no (3) 1 00001 1 synchronize (without data) no yes 1 00010 2 transmit status word no no 1 00011 3 initiate self-test no yes 1 00100 4 transmitter shutdown no yes 1 00101 5 override transmitter shutdown no yes 1 00110 6 inhibit terminal flag no yes 1 00111 7 override inhibit terminal flag no yes 1 01000 8 reset remote terminal no yes 1 01001 to 01111 9 to 15 reserved mode commands 9 - 15 with t/ r bit = 1 no yes (2) 0 10000 16 undefned mode command yes no (1) 1 10000 16 transmit vector word yes no 0 10001 17 synchronize with data yes yes 1 10001 17 undefned mode command yes no (1) 0 10010 18 undefned mode command yes no (1) HI-6130, hi-6131
holt integrated circuits 211 command t/ r bit mode code mil-std-1553 defned function associated data word broadcast allowed see note binary dec. 1 10010 18 transmit last command yes no 0 10011 19 undefned mode command yes no (1) 1 10011 19 transmit built-in test word yes no 0 10100 20 selected transmitter shutdown yes yes 1 10100 20 undefned mode command yes no (1) 0 10101 21 override selected transmitter shutdown yes yes 1 10101 21 undefned mode command yes no (1) 0 01001 to 01111 22 to 31 reserved mode commands 22 - 31 with t/ r bit = 0 yes yes (2) 1 01001 to 01111 22 to 31 reserved mode commands 22 - 31 with t/ r bit = 1 yes no (2) notes: 1. the 22 undefned mode commands can be rendered invalid by setting the umcinv (undefned mode codes invalid) option bit in confguration register1. if umcinv is asserted, there is no recognition of the undefned com - mand by the terminal. if umcinv is zero, the commands are considered valid. terminal response when umcinv equals 0 is wholly determined by the illegalization table: a. if a commands bit in the illegalization table equals zero, the terminal responds in form with clear status. mode commands 17, 20 and 21 are undefned when t/ r bit equals one, but will transmit a contiguous data word. mode commands 16, 18 or 19 are undefned when t/ r bit equals 0, but will receive a contiguous data word. b. if a commands bit in the illegalization table equals one, the command is considered illegal. the message error (me) status bit is asserted and the terminal transmits status without data word. illegal mode commands 16-31 will not transmit or receive a mode data word. 2. response to the reserved mode commands is fully defned by illegalization table settings. as described in (a) and (b) above, the terminal illegalizes any reserved mode command having illegalization table bit equal to 1, and re - sponds in form when the table bit equals zero. the in form response for reserved mode commands 16 through 31 transacts a received or transmitted data word. 3. HI-6130/31 cannot fulfll bus control duties. HI-6130, hi-6131
holt integrated circuits 212 21.4. standard mode command processing data buffer options for mode commands differ from buffer options for subaddress commands. mode commands can use ping-pong buffering or indexed buffering. when mode commands use indexed buffers, single message mode (indx = 0) is recommended. when using indexed or ping-pong buffers for mode commands: ? for mode commands without associated data word (mode codes 0-15 decimal), only the message information and time-tag words are updated in the mode commands assigned data buffer in ram. ? for mode commands 16-31 (decimal) that receive a data word, indexed and ping-pong buffer methods copy the received mode data word to the mode commands assigned data buffer in shared ram, after the message is transacted. the message information and time-tag words are also updated. ? for most mode commands 16-31 (decimal) that transmit a data word, the device reads the data word for transmit from the buffer location assigned in the descriptor table. exceptions occur for mc18 transmit last command and for mc19 transmit bit word. the mc18 data word is automatically provided by the device, based on recent command transactions. the mc19 data word for rt1 comes from register 0x1e or 0x1f, selected by the alt - bitw option in the rt1 confguration register (section 18.1). for rt2, the mc19 data word comes from register 0x27 or 0x28, selected by the altbitw option in the rt2 confguration register. for both mc18 and mc19, the transmitted data word is automatically recorded in the mode commands assigned data buffer in ram, after message completion. the message information and time-tag words are also updated. 21.5. simplifed mode command processing mode commands have a buffer alternative that is unavailable for subaddress commands. the smcp bit in the rt con - fguration register selects simplifed mode command processing, a global option applying to all mode commands. when the smcp bit is high, mode command descriptor blocks (in the descriptor table) do not contain data pointers to reserved buffers elsewhere in the shared ram. instead, each 4-word descriptor block itself contains the message information word, the time-tag word and the data from the most recent occurrence of each mode command: descriptor word 1 mode command control word descriptor word 2 message information word descriptor word 3 time-tag word descriptor word 4 mode data word descriptor word 1 contains the receive or transmit mode command control word. when smcp is used, just two con - trol word bits are used: dbac (descriptor block accessed) and bcast (broadcast). when smcp is enabled, the host need not initialize the mode code command segments in the descriptor table. when simplifed mode command processing is selected, the host does not write descriptor words 2-3 in the descriptor table entries for mode commands. for mode code values 0 to 15 decimal, the descriptor word 4 serves no function because these mode codes do not have an associated data word. for transmit mode code values 16 to 31, the host may initialize descriptor word 4. the default transmit value is 0x0000. mode command mc16 transmit vector word is one of the three defned mode commands that transmit a data word: mc16, mc18 and mc19. its descriptor word 4 should be initialized if a value other than 0x0000 is needed. mc18 and mc19 are discussed below. ? for mode commands without associated data word (mode codes 0-15 decimal), simplifed mode command processing updates the message information and time-tag words in descriptor words 2 and 3, and descriptor word 1 (bits 9,11). for these commands, smcp does not update descriptor word 4, which may be non-zero if written earlier by the host. ? for receive mode commands 16-31 (decimal) that receive a data word, simplifed mode command processing copies the received mode data word to descriptor word 4. the message information and time-tag words in descriptor words 2 and 3, and descriptor word 1 (bits 9, 11) are also updated. ? for most transmit mode codes 16-31 (decimal), the device reads the data word for transmission from each commands descriptor word 4. exceptions occur for mc18 transmit last command and for mc19 transmit built- in test word. the mc18 data word is automatically provided, based on the last command transacted. the mc19 HI-6130, hi-6131
holt integrated circuits 213 data word for rt1 comes from register 0x1e or 0x1f, selected by the altbitw option in the rt1 confguration register (section 18.1). for rt2, the mc19 data word comes from register 0x27 or 0x28, selected by the altbitw option in the rt2 confguration register. for mc18 and mc19, the transmitted data value is automatically copied to the mode commands descriptor word 4 after message completion. the message information and time-tag words in descriptor words 2 and 3, and descriptor word 1 (bits 9, 11) are also updated. the appendix shows terminal response to all possible subaddress and mode code command combinations. the table summarizes terminal response for the full range of message conditions, including errors, incomplete messages, etc. the table explicitly describes terminal response and impact on terminal status word, descriptor control words and data buffer message information words. the table includes effects for all pertinent setup options and identifes all interrupt options available. bold text blocks indicate error-free messages or in form clear status responses when the terminal is not using illegal command detection. HI-6130, hi-6131
holt integrated circuits 214 22. serial eeprom programming utility the HI-6130 or hi-6131 can program a serial eeprom via the dedicated eeprom spi port for subsequent auto- initialization events. the device copies host-confgured registers and ram (confguration tables and possibly data buffers) to serial eeprom. compatible spi serial eeproms are 3.3v, operate in spi modes 1 or 3 and have 128-byte pages. the serial spi data is clocked at 8.3 mhz sck frequency. a 2k x 8 eeprom can restore the lower 1k x 16 device address space. a 64k x 8 eeprom retains the entire 32k x 16 register/ram address space. 22.1. writing the auto-initialization eeprom a deliberate series of events initiates copy of data from HI-6130 or hi-6131 registers and ram to serial eeprom. this reduces the likelihood of accidental eeprom overwrites. the following series of events must occur to initiate programming: 1. using a fresh host initialization immediately following mr master reset as the basis for eeprom copy until eeprom reprogramming is complete, disconnect the terminal from mil-std-1553 buses, or take other measures to prevent bus activity detection by the device. with the autoen, txinha and txinhb pins in logic 0 state, apply mr master reset and wait for ready output assertion. verify that the irq interrupt output does not pulse low at ready assertion, indicating likely rt address parity error at the rta4:0 and rtap pins. using known good parameters, the host initializes device registers, the ram descriptor table and transmit data buffers (if necessary). ? if auto-initialization will be used to confgure the bus controller, the bcena input pin should be logic 1. the corresponding bcena bit 12 in master confguration register 0x0000 should be logic 1, but bcstrt register bit 13 must remain in the post-reset logic 0 state. ? if auto-initialization will be used to confgure the bus monitor, the mtrun input pin should be logic 1. the cor - responding mtena bit 8 in master confguration register 0x0000 should be logic 0. until eeprom program - ming is complete, the terminal should be disconnected from mil-std-1553 buses (or other measures taken) to prevent bus activity detection by the monitor. ? if auto-initialization will be used to confgure remote terminals rt1 and/or rt2, the rt1ena and/or rt2ena input pins should be logic 1. the corresponding rt1ena and/or rt2ena bits 6 and 7 in master confgura - tion register 0x0000 should be logic 1, but rt1stex and rt2stex register bits 4 and 5 must remain in the post-reset logic 0 state. skip to step 3. 2. using the existing eeprom confguration as the baseline for a new eeprom confguration until eeprom reprogramming is complete, disconnect the terminal from mil-std-1553 buses, or take other measures to prevent bus activity detection by the device. if the application includes the bus controller, the bcena input pin should be at logic 0. with the autoen pin in logic 1 state and the txinha and txinhb pins in logic 0 state, apply and release mr master reset and wait for ready output assertion. verify that the irq output does not pulse low (or go and remain low) at ready assertion. confrm that the eecke and ramif bits are logic 0 in the operational status register 0x0002. if register bits 4 or 5 (rt1stex, rt2stex) in master confguration register 0x0000 were set by auto-initialization, reset them now. modify register and ram values to refect the new changes. 3. if the application includes the bus controller, the bcena input pin should be set to logic 1 now. do not assert bcstrt bit 13 in master confguration register 0x0000. HI-6130, hi-6131
holt integrated circuits 215 eeprom programming is locked out at step 4 for the following conditions: ? active output pin assertion occurs after mr master reset. ? rt1stex bit 4, rt2stex bit 5 or mtena bit 8 is set in master confguration reg 0x0000. 4. the host writes a 2-part unlock code to ram address 0x004e. the unlock code value selectively enables any combination of terminal devices (bc, mt, rt1, rt2) to automatically start execution, after subsequent auto-initial - ization sequences are performed. programmed here, the same combination of terminal devices is simultaneously enabled after every initialization. unlock words are encoded as shown in table 18 . table 18. terminal unlock word encoding word 1 word 2 initialize rt1 2 initialize rt2 3 initialize mt 4 initialize bc 5 0xa00a 0x5ff5 no auto init. 1 no auto init. no auto init. no auto init. 0xa03a 0x5fc5 x 0xa0ca 0x5f35 x 0xa0fa 0x5f05 x x 0xa30a 0x5cf5 x 0xa33a 0x5cc5 x x 0xa3ca 0x5c35 x x 0xa3fa 0x5c05 x x x 0xac0a 0x53f5 x 0xac3a 0x53c5 x x 0xacca 0x5335 x x 0xacfa 0x5305 x x x 0xaf0a 0x50f5 x x 0xaf3a 0x50c5 x x x 0xafca 0x5035 x x x 0xaffa 0x5005 x x x x note 1 : default. no terminal devices (bc, mt, rt1, rt2) are started. the host must write master confguration register 0x0000 to start terminals. note 2 : the rt1ena register bit 6 in register 0x0000 must be set before step 4. during auto-initialization events, the rt1ena and autoen input pins must be logic 1 before rising edge of mr master reset. after auto-initialization, rt1stex bit 4 is automatically set in master confguration. register 0x0000, starting remote terminal rt1 execution. note 3 : the rt2ena register bit 7 in register 0x0000 must be set before step 4. during auto-initialization events, the rt2ena and autoen input pins must be logic 1 before rising edge of mr master reset. after auto-initialization, rt2stex bit 5 is automatically set in master confguration register 0x0000, starting remote terminal rt2 execution. note 4 : the mtena register bit 8 in register 0x0000 must be set before step 4. during auto-initialization events, the mtrun and autoen input pins must be logic 1 before rising edge of mr master reset. after auto-initialization, the smt or imt mtena bit is automatically set in master confguration register 0x0000, starting bus monitor execution. note 5 : the bcena register bit 12 in register 0x0000 must be set before step 4. during auto-initialization events, the bcena and autoen input pins must be logic 1 before rising edge of mr master reset. after auto-initialization, bcstrt bit 13 is automatically pulsed in master confguration register 0x0000, starting bus controller execution. HI-6130, hi-6131
holt integrated circuits 216 the four terminals can be automatically started (or not started) in any combination. for example, exclusive-oring both default unlock words 1 and 2 with 0x0ff0 results in unlock word 1 = 0xaffa and word 2 = 0x5005. this combination automatically and simultaneously enables execution for all four terminal devices: bc, mt, rt1 and rt2, at every subsequent auto-initialization from eeprom. individual soft resets for a single terminal device will automatically enable that device, if enabled here. 5. the eecopy input pin is driven high for at least 1 ms, then driven low. in response, the ready output goes low while eeprom memory is written. the unlock code at address 0x004e is cleared. device register and ram con - tents are written to the serial eeprom, one byte at a time. during programming, terminal checksums are tallied for the rt1, rt2 and smt/imt terminal devices, if used. an overall 32k checksum is also tallied. these checksums, stored in the eeprom, are used for error detection later, during auto-initialization and soft reset events. there is no bus controller soft reset. checksum type eeprom location corresponds to ram address overall checksum 0x004e rt1 checksum 0x01c0 rt2 checksum 0x01e0 smt or imt checksum 0x005c on the following pages, see the list of registers included in the stored overall and terminal checksums. when the ready output goes high, eeprom copy is complete. 6. for terminal devices selected for auto-enable by step 4 unlock word selection, the rt1stex, rt2stex, mtena and/or bcstrt bits are set in the 2-byte eeprom image corresponding to master confguration register 0x0000. during subsequent auto-initialization events, these are the last bits written, just before ready assertion. terminal devices having enable bits set to logic 1 in the eeprom image are automatically and simultaneously enabled just before ready assertion. terminal devices not automatically enabled (by step 4 unlock word selection) have logic 0 enable bits rt1stex, rt2stex, mtena and/or bcstrt in the 2-byte eeprom image corresponding to master confguration register 0x0000. after auto-initialization, these terminal devices remain in standby until enabled by host write to the master confguration register 0x0000. 22.2. overall 32k word checksum used by auto-initialization when auto-initialization is performed, the overall checksum (stored in eeprom by the eecopy process) is used for error checking. eecopy stored this checksum value in the two 8-bit locations corresponding to ram address 0x004e. this checksum covers the entire 32k word register and ram address range from 0 to 0x7fff, excluding the following register addresses. at auto-initialization, the following registers are not written using eeprom data: table 19. registers are not written using eeprom data address excluded register name 0x0002 master status & reset register 0x0007 bc pending interrupt register 0x0008 mt pending interrupt register 0x0009 rt1 & rt2 pending interrupt register 0x000a interrupt log address pointer HI-6130, hi-6131
holt integrated circuits 217 address excluded register name 0x000b rt1 memory address pointer 0x000c rt2 memory address pointer 0x000d mt memory address pointer 0x000e bc memory address pointer 0x0018 rt1 operational status register 0x001e rt1 built-in test word register 0x0021 rt2 operational status register 0x0027 rt2 built-in test word register 0x0030 mt current address pointer 0x0031 mt last address pointer 0x0035 bc frame time remaining register 0x0036 bc message time remaining register 0x0037 bc condition code register 0x003a mt time tag counter low 0x003b mt time tag counter mid 0x003c mt time tag counter high 0x0043 bc time tag counter low 0x0044 bc time tag counter high 0x0049 rt1 time tag counter 0x004b rt2 time tag counter the overall checksum includes individual terminal checksums for rt1, rt2 and bus monitor, which the eecopy process stored at eeprom locations corresponding to ram addresses 0x01c0, 0x01e0 and 0x005c respectively. all checksums stored by the eecopy process use twos complement format. each checksum is calculated by summing the individual 16-bit data values (ignoring carry) over the full set of included register and ram addresses. the summa - tion is then complemented, then incremented (ignoring carry) to yield the stored twos complement checksum value. when the device performs checksum-based error checking, a new summation is tallied (ignoring carry) for the indi - vidual 16-bit data values over the range of included register and ram addresses. when this summation is added to the previously stored twos complement checksum, the result is zero when the new data summation is the same as that tallied by eecopy when the checksum was stored. the registers tallied in each of the rt1, rt2 and smt or imt terminal checksums are summarized on the next pages. these individual checksums are used for error checking during soft reset events. soft reset occurs for rt1, rt2 or smt / imt when rt1reset bit 10, rt2reset bit 11 and/or mtreset bit 12 is set in the master status and reset register 0x0001. one, two or three terminal reset bits can be individually or simultaneously set, without affecting other on-chip terminals or the bus controller. the hi-613x bus controller does not have soft reset. HI-6130, hi-6131
holt integrated circuits 218 23. reset and initialization this section describes the software reset mechanisms. hardware master reset returns the device to the uninitialized state, requiring register and ram initialization before terminal execution can begin. hardware reset is initiated by assertion of the mr master reset pin (200ns minimum assertion time). software reset is individually or simultaneously asserted for the bus monitor, rt1 or rt2 by setting the corresponding bit(s) in the master status and reset register. the bus controller does not have software reset. if autoen is enabled, both hardware and software reset copy initialization values from eeprom into registers and ram. 23.1. hardware master reset and optional auto-initialization hardware master reset is initiated by a low to high transition on the mr pin; it should be applied after power-up, but may be used any time afterward. when asserted, the mr input pin causes immediate unconditional hardware reset for all device terminals. command processing is terminated and reset, the bus decoders and encoders are cleared, and all time tag counters are reset. all internal logic is cleared. registers are restored to the power up reset states shown in table 5 . the ready, active and irq output pins are negated if previously asserted. the ready pin remains low until the entire reset process is complete. during this interval, a host read cycle to any address returns the value of the master status and reset register 0x0002. after a low to high transition on the mr pin, these events occur: 1. after 200ns, input states for the rt1a4-rt1a0, rt1ap and rt1lock pins are latched into the rt1 operational status register 0x0018. input states for the rt2a4-rt2a0, rt2ap and rt2lock pins are latched into the rt2 operational status register 0x0021. the input state for the autoen pin is latched into the master status and reset register 0x0002. 2. at master reset, there are four pin-selected combinations for ram self-test on/off and auto-initialize on/off. for the 4 combinations, hardware mr rising edge to ready assertion times are summarized in the following table. table 20. ready delay times: from mr input pin rising edge to ready output pin rising edge combinations mtstoff pin state autoen pin state ready delay (s) no ram test, no auto-initialize 1 0 164 perform ram test, no auto-initialize 0 0 1480 no ram test, auto-initialize 1 1 63,100 perform ram test, auto-initialize 0 1 64,400 if memory error occurs, the bmtf bits are set in the rt1 bit word and rt2 bit word registers. if the mtstoff pin is logic 1, the ram test is bypassed. this option might be chosen if a faster reset process is needed. regard - less of the mtstoff pin state, all ram locations above address 0x004f are reset to 0x0000. 3. after internal processes are initialized, the device checks the state of the autoen bit latched into the master status and reset register 0x0002 at step 1: if the autoen bit in the master status and reset register 0x0002 is logic 0, auto initialization from eeprom is bypassed. after the ram memory test is complete, the device asserts the ready output pin to indicate that the device is ready for host initialization of registers and ram: ? the master confguration register 0x0000 is initialized to indicate which terminal devices are enabled (bcena, rt1ena and rt2ena). the corresponding input pins must already be logic 1, or these register bits cannot be set. if using bus monitor, the mtrun input pin should be logic 1 but the corresponding mtena register bit should remain logic 0 until initialization is completed. likewise, the bcstart, rt1stex and rt2stex bits remain low at this time. ? other confguration registers are initialized by the host to defne interrupt behavior and time tag counter behavior for enabled terminal devices. HI-6130, hi-6131
holt integrated circuits 219 ? if using rt1 and/or rt2, the following registers are initialized: the rt confguration register(s), the rt descrip - tor table base address register(s), the rt bus a/b select register(s) and the rt interrupt enable register. in ram, the rt illegalization table(s) and rt descriptor table(s) are initialized. initial data for assigned transmit subaddress data buffers may be initialized at this time. ? if using the bus controller, the bc confguration, bc instruction list start address and bc interrupt enable reg - isters are initialized. in ram, the bc instruction list and bc message control blocks are initialized. ? if using a simple bus monitor, the mt confguration, smt address list start address and smt interrupt enable registers are initialized. in ram, the smt address list and smt filter table are initialized. ? if using an irig-106 bus monitor (imt), the following registers are initialized: the imt confguration register, the imt address list start address register, the imt packet max message count register, the imt packet max word count register, the imt max packet time register, the imt max gap time register, the imt channel id register and the imt interrupt enable register. in ram, the imt address list and imt filter table are initialized. ? upon completing all initialization for registers and ram, the host writes the master confguration register 0x0000 to start operation for the enabled terminal devices. a combination of bcstart, rt1stex, rt2stex and/or mtena register bits are asserted to match the subset of initialized terminal devices (bc, rt1, rt2 and mt). device operation begins. if the autoen bit in the master status and reset register 0x0002 is logic 1, auto initialization from eeprom is performed after completion of the ram memory test. the ready output pin remains at logic 0 during the self-initial - ization process. initialization data is read from the previously-written external eeprom and copied to the entire range of registers and ram, from address 0x0000 to address 0x7fff. this process typically requires 63 ms (see table 20 ). during auto initialization, the written value for each register or ram location is read back for confrmation. if the value read fails to match the corresponding value in eeprom, an initialization error is saved. this error results in action taken later when the initialization process is fnished. while performing initialization a running checksum is tallied. a properly-confgured serial eeprom contains a 16-bit checksum value stored at the eeprom byte pair locations corresponding to ram address 0x004e. the stored check - sum is tallied as if ram address 0x004e equals zero, and twenty-fve register locations listed in table 19 are also excluded from the stored checksum value. the stored value is actually the twos complement of the 16-bit memory checksum, ( checksum + 1). as each individual register and ram location is initialized, its written value is added to a copy of the stored checksum value from eeprom. if all locations match at the end, the running checksum tally added to the twos complemented eeprom checksum should equal zero. after initialization, when ready is asserted, the 16-bit twos complement checksum value is copied from eeprom to device ram address 0x004e. if an initialization error occurred, the following events take place immediately after ready assertion: ? the irq interrupt output pin is asserted. ? the master status and reset register 0x0001 is written to indicate type of error. if checksum failure, the eeckf register bit is asserted. if data mismatch between eeprom and read back ram value, the ramif register bit is asserted. ? the eelf bit is asserted in the rt1 built-in test word register and in the rt2 built-in test word register. ? if ramif read back error occurred, the address of the frst occurring instance is written to register address 0x0024. see section 23.2. memory test fail address register (0x0024) on page 221 for further information. additional locations beyond the saved address may have mismatch, but only the frst instance is logged. after copying the full range of register and ram addresses, the rt1stex, rt2stex and mtena bits in the master confguration register 0x0000 are still zero. in the same register, the bcstart bit always reads zero, but the bcac - tive bit in the master status and reset register 0x0001 is still zero. the eeprom is written using methods described in section 22.1 . each of the four terminal devices can indepen - dently be confgured to self-start when error-free auto-initialization is complete, or not self-start, requiring a host write HI-6130, hi-6131
holt integrated circuits 220 to the master confguration register after ready assertion. in the eeprom byte pair corresponding to master con - fguration register 0x0000: ? if the eeprom rt1stex and rt1ena bits are both logic 1, and if the rt1ena pin is also high, and if the rt1apf bit is logic 0 in the rt1 operational status register, remote terminal 1 will automatically start just be - fore ready assertion. once rt1 is started, the master confguration register rt1stex bit will read logic 1. if the eeprom rt1stex bit is logic 0, the host must write the master confguration register rt1stex bit high after ready assertion to start remote terminal 1. the rt1ena register bit and input pin must both be logic 1 before rt1stex assertion. ? if the eeprom rt2stex and rt2ena bits are both logic 1, and if the rt2ena pin is also high, and if the rt2apf bit is logic 0 in the rt2 operational status register, remote terminal 2 will automatically start just be - fore ready assertion. once rt2 is started, the master confguration register rt2stex bit will read logic 1. if the eeprom rt2stex bit is logic 0, the host must write the master confguration register rt2stex bit high after ready assertion to start remote terminal 2. the rt2ena register bit and input pin must both be logic 1 before rt2stex assertion. ? if the eeprom bctrig bit is logic 1, and if the bcena input pin is also high, the bus controller will automati - cally start just before ready assertion. once the bc is started, the master confguration register bctrig and bcstart bits will continue to read logic zero, but the bcactive bit in the master status and reset register 0x0001 will read logic 1. if the eeprom bctrig bit is logic 0, the host must assert the master confguration register bcstart bit after ready assertion to start the bus controller. the bcena input pin must be logic one before bcstart assertion. the bcstart register bit self-resets, but the bcactive bit in the master status and reset register 0x0001 will read logic 1. ? if the eeprom mtena bit is logic 1, and if the mtrun input pin is also high, the bus monitor will automatically start just before ready assertion. once the bus monitor is started, the master confguration register mtena will read logic 1. if the eeprom mtena bit is logic 0, the host must write the master confguration register mtena bit high after ready assertion to start the bus monitor. the mtrun input pin must be logic 1 before mtena assertion. note that automatic-self-start for rt1 and rt2 requires the corresponding rtapf status bit to be logic 0 in the rt operational status register. this indicates valid odd parity for the terminal address and parity bits latched in the rt operational status register, not necessarily the state of the rt address and parity pins. because auto-initialization follows master reset, the mirrored pin states latched at reset is overwritten by eeprom values if rtxlock input pin is logic 0. ? when the rt1lock or rt2lock input pin is logic 1 at master reset rising edge, the corresponding rt operational status register terminal address and parity bits refect address input pin states 200ns after reset rising edge. ? when the rt1lock or rt2lock input pin is logic 0 at master reset rising edge, the latched rt address, parity and rtxlock bit values are overwritten by values from the initialization eeprom. if automatic-self-start for rt1 or rt2 was blocked due to invalid odd parity for the terminal address and parity bits latched in the rt operational status register, the rt1stex or rt2stex bit cannot be asserted in the master confg - uration register until the parity error is corrected. the host may overwrite the rt1 or rt2 operational status register to correct the parity error, then assert rt1stex or rt2stex in the master confguration register. if automatic-self-start for terminal devices was blocked due to ramif or eeckf auto-initialization errors, the host can override the error condition after ready assertion by setting the rt1stex, rt2stex, bcstart and/or mtena bits in the master confguration register, providing the other operational conditions (in the 4-bullet list above) are met. a method for programming the initialization eeprom from a fully con f gured terminal is explained in section 22 . if a different method is used for writing the serial eeprom, for successful self-initialization after master reset, the twos- complemented checksum (described earlier) must be saved in eeprom locations corresponding to device ram ad - dress 0x004e. if a different method is used for writing the serial eeprom, in order to perform soft resets, twos-complement checksum must be written for remote terminal 1 at 0x01c0, remote terminal 2 at 0x01e0 and the monitor terminal at 0x005c. HI-6130, hi-6131
holt integrated circuits 221 a compatible serial eeprom uses a spi interface for byte-access read and write operations. sixteen-bit register and ram values in the hi-613x are stored as upper and lower bytes in the eeprom, in big endian fashion. for example, the upper byte for register address 0x0000 is stored at eeprom address 0x0000 while the lower byte is stored at eeprom address 0x0001. a 64k x 8 eeprom is required to store the entire 32k x 16 address range. serial eeprom data mapping follows the device memory map shown in figure 2. the four exceptions: 1. the two eeprom bytes corresponding to device ram address 0x004e must contain the expected overall check - sum value and if software resets are expected 2. the two eeprom bytes corresponding to device ram address 0x01c0 must contain the expected terminal check - sum value for remote terminal 1 3. the two eeprom bytes corresponding to device ram address 0x01e0 must contain the expected terminal check - sum value for remote terminal 2 4. the two eeprom bytes corresponding to device ram address 0x005c must contain the expected terminal check - sum value for the bus monitor. the serial eeprom used for auto-initialization should be fully written to cover the HI-6130/31 upper address limit of 0x7fff. ideally the eeprom image re f ects a post-mr reset followed by fresh initialization by the host, with nothing written to reset-cleared registers or ram as a result of command processing. 23.2. memory test fail address register (0x0024) msb 0 0 0 0 0 0 0 0 0 0 0 0 0 0 rw 0 0 memory test fail address register mr reset host access bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 lsb if the autoen input pin is logic 1, auto-initialization from eeprom is enabled. when one or more initialized ram locations do not match their two corresponding serial eeprom byte locations, ramif bit 13 is set in the hardware pending interrupt register 0x0006, as well as ramif bit 0 in the master status and reset register 0x0001. such failure may occur during auto initialization, or execution of a partial reset caused by assertion of the rt1reset, rt2reset or mtreset bits in the master status and reset register, 0x0001. the address of the frst occurring ram/eeprom mismatch is written to the memory test fail address register, 0x0024. additional locations beyond the saved address may have mismatch, but just the frst instance is logged and the test stops. once terminal operation starts, register 0x0024 reverts to its normal function, the rt2 current message info word register, if terminal rt2 is enabled. HI-6130, hi-6131
holt integrated circuits 222 23.3. software reset 23.3.1. remote terminal 1 (rt1) this is initiated when rt1reset bit 10 is set in the master status and reset register 0x0001. the following actions are performed. table 21. rt1 soft reset summary action registers affected clears these individual register bits 0x0000 master confguration register, rt1stex bit 4 0x0006 hardware pending int register, rtip bit 2 0x0006 hardware pending int register, rt1apf bit 3 0x0009 rt1 and rt2 pending int register, rt1 int bits 8 C 3 clears these entire register addresses 0x0018 rt1 operational status register 0x001a rt1 mil-std-1553 status word bits register 0x001e rt1 built-in test word register 0x0049 rt1 time tag counter loads these registers from eeprom these 522 locations comprise the rt1 terminal checksum stored at 0x01c0 by eecopy process 0x000f hardware interrupt enable register 0x0012 rt1 & rt2 interrupt enable register (see note) 0x0013 hardware interrupt output enable register 0x0016 rt1 & rt2 interrupt output enable register (see note) 0x0017 rt1 confguration register 0x0019 rt1 descriptor table base address register 0x001c rt1 bus a select register 0x001d rt1 bus b select register 0x001f rt1 alternate bit word register 0x004a rt1 time tag utility register 0x0200 through 0x02ff: rt1 illegalization table 0x0400 through 0x05ff: rt1 descriptor table note: this register reload potentially affects both rts. rt1 automatically starts (rt1stex is set in register 0x0000) after soft reset completion, if these requirements are met: ? the rt1ena pin is logic 1 during the soft reset event ? the rt1ena pin and rt1ena bit 6 were both logic 1 in the master confguration register when eecopy created the eeprom image. ? the rt1stex bit 4 is logic 1 in the eeprom master confguration register image because the eecopy unlock codes during programming were unlock word 1 = 1010-xxxx-xx11-1010 and unlock word 2 = 0101-xxxx- xx00-0101 where x denotes dont care. to manually start rt1 after soft reset completion (indicated by ready signal assertion), the host must set rt1stex bit 4 in register 0x0000, if rt1 auto-start was disabled or otherwise failed for one or more of these reasons: ? the rt1ena pin was logic 0 during the soft reset event. ? the rt1ena pin was logic 0 and/or rt1ena bit 6 was logic 0 in the master confguration register when HI-6130, hi-6131
holt integrated circuits 223 eecopy created the eeprom image. a new eeprom image is needed to allow auto-start after rt1 soft reset. ? the rt1stex bit 4 is logic 0 in the eeprom master confguration register image because the unlock codes used by eecopy were wrong. a new eeprom image is needed to allow auto-start after rt1 soft reset. 23.3.2. remote terminal 2 (rt2) this is initiated when rt2reset bit 11 is set in the master status and reset register 0x0001. the following actions are performed. table 22. rt2 soft reset summary action registers affected clears these individual register bits 0x0000 master confguration register, rt2stex bit 3 0x0006 hardware pending int register, rtip bit 2 0x0006 hardware pending int register, rt2apf bit 4 0x0009 rt1 and rt2 pending int register, rt2 int bits 15 C 10 clears these entire register addresses 0x0021 rt2 operational status register 0x0023 rt2 mil-std-1553 status word bits register 0x0027 rt2 built-in test word register 0x004b rt2 time tag counter loads these registers from eeprom these 522 locations comprise the rt2 terminal checksum stored at 0x01e0 by eecopy process 0x000f hardware interrupt enable register 0x0012 rt1 & rt2 interrupt enable register (see note) 0x0013 hardware interrupt output enable register 0x0016 rt1 & rt2 interrupt output enable register (see note) 0x0020 rt2 confguration register 0x0022 rt2 descriptor table base address register 0x0025 rt2 bus a select register 0x0026 rt2 bus b select register 0x0028 rt2 alternate bit word register 0x004c rt2 time tag utility register 0x0300 through 0x03ff: rt2 illegalization table 0x0600 through 0x07ff: rt2 descriptor table note: this register reload potentially affects both rts. rt2 automatically starts (rt2stex is set in register 0x0000) after soft reset completion, if these requirements are met: ? the rt2ena pin is logic 1 during the soft reset event ? the rt2ena pin and rt2ena bit 7 were both logic 1 in the master confguration register when eecopy created the eeprom image. ? the rt2stex bit 5 is logic 1 in the eeprom master confguration register image because the eecopy unlock codes during programming were unlock word 1 = 1010-xxxx-11xx-1010 and unlock word 2 = 0101-xxxx- 00xx-0101 where x denotes dont care. to manually start rt2 after soft reset completion (indicated by ready signal assertion), the host must set rt2stex HI-6130, hi-6131
holt integrated circuits 224 bit 5 in register 0x0000, if rt1 auto-start was disabled or otherwise failed for one or more of these reasons: ? the rt2ena pin was logic 0 during the soft reset event ? the rt2ena pin was logic 0 and/or rt2ena bit 7 was logic 0 in the master confguration register when eecopy created the eeprom image. a new eeprom image is needed to allow auto-start after rt2 soft reset. ? the rt2stex bit 5 is logic 0 in the eeprom master confguration register image because the unlock codes used by eecopy were wrong. a new eeprom image is needed to allow auto-start after rt2 soft reset. 23.3.3. bus monitor smt / imt this is initiated when mtreset bit 12 is set in the master status and reset register 0x0001. the following actions are performed. table 23. smt / imt soft reset summary action registers affected clears these individual register bits 0x0000 master confguration register, mtena bit 8 0x0006 hardware pending int register, mtip bit 1 clears these entire register addresses 0x0008 mt pending interrupt register 0x0030 mt next message buffer address pointer 0x0031 mt last message buffer address pointer 0x003a mt time tag counter, low 0x003b mt time tag counter, mid 0x003c mt time tag counter, high loads these registers from eeprom these 561 locations comprise the mt terminal checksum stored at 0x005c by eecopy process 0x000f hardware interrupt enable register 0x0011 mt interrupt enable register 0x0013 hardware interrupt output enable register 0x0015 mt interrupt output enable register 0x0029 mt confguration register 0x002a imt packet maximum message count register 0x002b imt packet maximum mil-std-1553 word count register 0x002c imt packet maximum time register 0x002d imt packet maximum gap time register 0x002e imt packet channel id register 0x002f mt buffer address table start address register 0x003d mt time tag utility register, low 0x003e mt time tag utility register, mid 0x003f mt time tag utility register, high 0x0040 mt time tag match register, low 0x0041 mt time tag match register, mid 0x0042 mt time tag match register, high 0x00b0 through 0x00bf: mt buffer address table(s) 0x0100 through 0x017f: mt message filter table note: soft reset for the bus monitor re-initializes the buffer address pointers, but does not clear the allocated buffer space in the buffer(s). HI-6130, hi-6131
holt integrated circuits 225 the bus monitor automatically starts (mtena is set in register 0x0000) after soft reset completion, if the following requirements are met. message recording commences when a new valid command is received: ? the mtrun pin is logic 1 during the soft reset event ? the mtrun pin was logic 1 in the master confguration register when eecopy created the eeprom image. ? the mtena bit 12 is logic 1 in the eeprom master confguration register image because eecopy used these unlock codes during eeprom programming: unlock word 1 = 1010-xx11-xxxx-1010 and unlock word 2 = 0101-xx00-xxxx-0101 where x denotes dont care. to manually start the bus monitor after soft reset completion (indicated by ready signal assertion), the host must set mtena bit 12 in register 0x0000, if auto-start was disabled or otherwise failed for one or more of these reasons: ? the mtrun pin was logic 0 during the soft reset event ? the mtrun pin was logic 0 in the master confguration register when eecopy created the eeprom image. a new eeprom image is needed to allow auto-start after mt soft reset. ? the mtena bit 12 is logic 0 in the eeprom master confguration register image because the unlock codes used by eecopy were wrong. a new eeprom image is needed to allow auto-start after bus monitor soft reset. HI-6130, hi-6131
holt integrated circuits 226 24. self-test the hi-613x provides several host-directed ram self-tests, as well as an automatic (but optional) ram self-test performed after master reset. in addition, on-line analog and off-line digital transmit/receive loopback tests are provided, with different options for bc and rt terminal modes. 24.1. optional ram self-test after hardware master reset when the mtstoff input pin is logic 0, the hi-613x device automatically performs ram self-test after each hardware master reset, following the rising edge of mr input signal. see section 23.1. hardware master reset and optional auto-initialization . the ready output pin goes low at mr assertion. ready remains low after mr rising edge and during ram self-test. the ram self-test performed is the increment/decrement (inc/dec) method described on page 231 . when successful ram self-test is complete, the ready output pin goes high, indicating that device registers and ram can be confgured for operation. the entire ram address space from 0x0050 to 0x7fff is cleared to 0x0000. ram self-test after hardware master reset is optional. if the mtstoff input pin is logic 1, ram testing is skipped, speeding up ready assertion. table 20 on page 218 shows the reset timing options. 24.2. host-directed self-test the hi-613x device supports host-directed ram self-test (sometimes called ram built-in self-test, or ram bist) and single-word transmit/receive loopback, which may be off-line digital or on-line analog. host-directed self-test is confgured and operated using register read/write operations. the host initiates self-test mode by asserting the test input pin to logic 1. when the test pin is high, four registers are active for performing ram self-test or rt mode loopback self-tests: 24.2.1. self-test control register (0x0028) not used not used 0 15 14 13 12 11 10 host access 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r r 0 mr reset rw bit 9 8 7 6 5 4 3 2 1 0 rbfail rbsel2 rbffail rbstrt frama rbsel1 rbsel0 rbpass lbstart lbpass lbfail lbbusel lbalog lbsync rw the function of this register is multiplexed by the device test input pin. when the test pin is logic 0 (normal operating mode) and the rt2ena input pin is logic 1, register address 0x0028 functions as the rt2 alternate bit word register described in section 18.11 on page 155 . when the test input pin is logic 1, register address 0x0028 functions as the self-test control register, a read-write register used for ram memory testing, or analog or digital loopback tests. bits 0, 1, 8, 9 are read-only. the remaining bits in this register are read-write. after test completion, the test input pin should be reset to logic 0, restoring all register bits to read-write. if using remote terminal rt2, the host should restore the desired alternate bit word value for rt2 at register address 0x0028. descriptions below apply when the test input pin is logic 1; the register is operating as the self-test control register. this register supports two types of test: register bits 15 - 8 are used for ram built-in self test (ram bist). register bits 7 - 2 are used for transceiver loopback testing (either digital loopback or analog loopback). under internal logic control, this device uses one ram self test (inc / dec test described below) to check internal ram memory after every mr pin master reset, unless the mtstoff input pin is logic 1. this option may be used to speed up reset completion. self-test control register bits 15 - 8 provide a means for the host to perform ram self-test at HI-6130, hi-6131
holt integrated circuits 227 other times. register bits 13:11 select ram test type. then bit 10 assertion starts the selected ram test, and bits 9-8 report a pass/fail result after test completion. all tests are destructive, overwriting data present before test commence - ment. note: reset refers to bit value following either master reset ( mr ) or software reset. bit no. mnemonic r/w reset function 15 frama r/w 0 full ram access enable. during normal operation, some bits in certain ram locations (e.g., descrip - tor table control words) cannot be written by the host. when the frama bit is asserted, host writes to ram are unrestricted to permit full testing. during normal completion, this bit must be reset to logic 0. 14 rbffail r/w 0 ram bist force failure. when this bit is asserted, ram test failure is forced to verify that ram bist logic is functional. 13,12,11 rbsel2:0 r/w 0 ram bist select bits 2-0. this 3-bit feld selects the ram bist test mode applied when the rb - start bit is set: rbsel2:0 selected ram test test time 000 idle - 001 pattern test, described below 14.42ms 010 write 0x0000 to ram address range 0x0000 - 0x7fff 170s 011 read and verify 0x0000 over ram address range 0x0000 - 0x7fff 500s 100 write 0xffff to ram address range 0x0000 - 0x7fff 170s 101 read and verify 0xffff over ram address range 0x0000 - 0x7fff 500s 110 inc / dec test performs only steps 5 - 8 of the pat - tern test below 1.32ms 111 idle - HI-6130, hi-6131
holt integrated circuits 228 bit no. mnemonic r/w reset function 13,12,11 rbsel2:0 (continued) r/w 0 description of the ram bist pattern test selected when register bits rbsel2:0 = 001: note: test read /write accesses to addresses 0x0000 - 0x0050 involve 81 ram locations not accessible to the host. these accesses do not affect the host-accessible registers, overlaying the same address range. 1. write 0x0000 to all ram locations, 0x0000 through 0x7fff. 2. repeat the following sequence for each ram location from 0x00000 through 0x7fff: a. read and verify 0x0000 b. write then read and verify 0x5555 c. write then read and verify 0xaaaa d. write then read and verify 0x3333 e. write then read and verify 0xcccc f. write then read and verify 0x0f0f g. write then read and verify 0xf0f0 h. write then read and verify 0x00ff i. write then read and verify 0xff00 j. write 0x0000 then increment ram address and go to step (a) 3. write 0xffff to all ram locations, 0x0000 through 0x7fff 4. repeat the following sequence for each ram location from 0x00000 through 0x7fff: a. read and verify 0xffff b. write then read and verify 0x5555 c. write then read and verify 0xaaaa d. write then read and verify 0x3333 e. write then read and verify 0xcccc f. write then read and verify 0x0f0f g. write then read and verify 0xf0f0 h. write then read and verify 0x00ff i. write then read and verify 0xff00 j. write 0xffffthen increment ram address and go to step (a) 5. write each cells memory address into each ram location from 0x00020 to 0x7fff. 6. read each memory location from 0x00000 to 0x7fff and verify it con - tains its address. 7. write 1s complement of each cells memory address, into each ram location (same addr range). 8. read each memory location and verify it contains the 1s complement of its address. 10 rbstrt r/w 0 ram bist start. writing logic 1 to this bit initiates the ram bist test selected by register bits rbsel2:0. the rbstrt bit can only be set if the test input pin is high and if register bit 15 is already asserted. this bit is automatically cleared upon test completion. register bits 9-8 indicate pass / fail test result. HI-6130, hi-6131
holt integrated circuits 229 bit no. mnemonic r/w reset function 9 rbpass r 0 ram bist pass. device logic asserts this bit when the selected ram test completes without error. this bit is automatically cleared when rbstrt bit 10 is set. 8 rbfail r 0 ram bist fail. device logic asserts this bit when failure occurs while performing the selected ram test. this bit is automatically cleared when rbstrt bit 10 is set. when bist failure occurs, a clue to the failing ram address can be read at register address 0x001b. for speed, the ram bist concurrently tests 4 quadrants of the ram address range, in parallel. if test failure occurs, register address 0x001b contains the ram address being tested in the lowest ram quadrant. actual failure has occurred in any of these four locations: at ram address addr stored in register 0x001b, or addr+0x2000, or addr+0x4000 or addr+0x6000. when the test input pin is logic 0, register address 0x001b function reverts to the read-only rt1 current message information word register described in section 18.7 on page 152 . 7,6 ----- r 0 not used. these bits cannot be set. a read will return 0-0. 5 lbalog r/w 0 loopback test analog. the device supports either digital or analog loopback testing for either bus transceiver. when the lbalog bit is low, digital loopback is selected and no data is transmitted onto the selected external mil-std-1553 bus. when the lbalog bit is high, analog loopback is selected and a test word is transmitted onto and received from the selected external mil-std-1553 bus. 4 lbsync r/w 0 loopback test word sync select. when the lbsync bit is high, the loopback test word is transmitted with command sync. when the lbsync bit is low, the loopback test word is transmitted with data sync. 3 lbbusel r/w 0 loopback test bus select. when this bit is low, loopback testing occurs on bus a. when this bit is high, loopback testing occurs on bus b. 2 lbstart r/w 0 loopback test start. writing logic 1 to this bit initiates the loopback test selected by register bits 3, 4 and 5. the lbstrt bit can only be set if the external test pin is al - ready asserted, and is automatically cleared upon test completion. register bits 1,0 indicate pass / fail test result. 1 lbpass r 0 loopback test pass. device logic asserts this bit when the selected ram test completes without error. this bit is automatically cleared when lbstart bit 2 is set. 0 lbfail r 0 loopback test fail. device logic asserts this bit when failure occurs while performing the selected loopback test. failure is comprised of manchester encoding error, parity error, wrong sync type or data mismatch. this bit is automatically cleared when lbstart bit 2 is set. HI-6130, hi-6131
holt integrated circuits 230 24.2.2. loopback test transmit data register (0x001f) msb 0 0 0 0 0 0 0 0 0 0 0 0 0 0 rw 0 0 loopback test transmit data register mr reset host access bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 lsb this register is cleared after mr pin master reset, but is not affected by srst software reset. the function of this register is multiplexed by the device test input pin. when test is logic 0 (normal operating mode) and the rt1ena input pin is logic 1, register address 0x001f is the rt1 alternate bit word register described in section 18.11 on page 155 . when the test input pin is logic 1, register address 0x001f becomes the loopback test transmit data register, a read-write register used for analog or digital loopback tests. when a loopback test is performed, the value in this register is transmitted, and should appear in the loopback test receive data register 0x0002. see section 24.2.1. self-test control register (0x0028) on page 226 (bits 0-5) for additional information. after test completion, the test input pin should be reset to logic 0. if using remote terminal rt1, the host should restore the desired alternate bit word value for rt1 at register address 0x001f. 24.2.3. loopback test receive data register (0x0002) msb 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r 0 0 loopback test receive data register mr reset host access bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 lsb this register is cleared after mr pin master reset, but is not affected by srst software reset. the function of this register is multiplexed by the device test input pin. when the test input pin is logic 0 (normal operating mode) and the rt1ena input pin is logic 1, register address 0x0002 is the rt1 current command register described in section 18.3 on page 150 . when the test input pin is logic 1, register address 0x0002 becomes the loopback test receive data register, a read-only register used for analog or digital loopback tests. when loop back is performed, the value in the loopback test transmit data register 0x001f is transmitted and should appear in this register. see section 24.2.1. self-test control register (0x0028) on page 226 (bits 0-5) for additional information. after test completion, the test input pin should be reset to logic 0, reverting this register address 0x0002 to the read- only rt1 current command register. the contained register value will not have meaning until rt1 receives its next valid command. 24.2.4. ram self-test fail address register (0x001b) msb 0 0 0 0 0 0 0 0 0 0 0 0 0 0 rw 0 0 ram bist fail address register mr reset host access bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 lsb upon test completion, self-test control register bit 9 (see section 24.2.1. self-test control register (0x0028) on page 226 ) is set if the test passed, otherwise bit 8 is set if the test failed. if failure occurs, the frst failed ram address is written to the ram bist fail address register. (this is actually an offset value within a memory quadrant; see the self-test control register bit 8 description.) memory test fail also asserts the btmf (bist memory test fail) bit 3 in both rt1 and rt2 bit word registers, at addresses 0x001e and 0x0027 respectively. HI-6130, hi-6131
holt integrated circuits 231 at test completion, the host should clear the self-test control register 0x0028, and then reset the test input pin to logic 0. 24.2.5. host-directed ram self-test host-directed ram self-test overwrites preexisting ram contents and should only be performed when complete re- confguration of the ram address space will occur after ram test completion. if the device is operational, terminal execution should be stopped. if asserted, reset bits 4-8 and bit 12 in 9.1. master confguration register (0x0000) , stopping bc, mt, and rt1-2. or, reset the bcena, rt1ena, rt2ena and mtrun input pins, if asserted. assert the test pin to activate register 0x0028 as the self-test control register. after asserting the test input pin, ram self-test is confgured and started by writing bits 15:10 in the self-test control register, described on page 226 . register bits 13:11 select one of the fve test protocols. register bit 15 is usually set to provide unrestricted ram read/write access. register bit 10 is then asserted to start the ram test selected by bits 13:11. all of these bits may be written simultaneously, and bits 7:0 should be written as zeros. test time varies based on complexity; test times are shown in the self-test control register description. upon ram test completion, self-test control register bit 9 is set if the ram test was successful, otherwise bit 8 is set if the test failed. if failure occurs, the frst failed ram address is written to the ram self-test fail address register 0x001b. the written value is actually an offset value within a memory quadrant; see the data sheet description for self-test control register, bit 8. memory test fail also asserts the btmf (bist memory test fail) bit 3 in the bit word register 0x0014. at ram test completion, the host should clear the self-test control register 0x0028, reset the test input pin to logic 0, then re-initialize registers and ram, and fnally restart terminal execution. 24.2.6. host-directed rt-mode loopback testing (on-line analog or off-line digital) rt mode loopback testing involves transmission and reception of a single manchester-encoded word with correct parity. on-line analog loopback transmits the specifed test word onto the external mil-std-1553 bus. the internal receiver for the same bus is totally independent from the encoder logic used for bus transmission. the bus receiver detects and decodes the received replica of the transceivers own transmission. off-line digital loopback does not disturb the selected mil-std-1553 bus; the digital signal paths used for encoding and transmission (as well as reception and decoding) are fully tested without involving the external mil-std-1553 bus; only the analog bus driver and analog receiver are bypassed for digital loopback tests. the hi-613x cannot be confgured for loopback transmitting on one bus and receiving on the other bus. rt mode loopback testing requires one or both rts to be enabled. if rt1 is not already running, assert the rt1ena pin and set the rt1ena bit in 9.1. master confguration register (0x0000) . then set the rt1stex bit in register 0x0000. rt2 can similarly be enabled, if desired. then initiate test mode by asserting the test input pin to logic 1. write a 16-bit transmit value to the loopback test transmit data register 0x001f. with the test input set to logic 1, the host can write bits 5:3 in the self-test control register 0x0028 to select analog or digital loopback, command sync or data sync, and select test bus a or bus b. then, without modifying bits 5:3, write the self-test control register again to set bit 2, starting loopback test. note: self-test control register bits 5:2 can be written simultaneously; the remaining register bits 15:6 and 1:0 should all be written as zeros. after 20s or so, rt loopback transmission is complete. self-test control register bit 1 is set for successful loopback test, otherwise bit 0 is set if loopback failed. the received word has been written into the loopback test receive data register 0x0002. it should match the value in the loopback test transmit data register 0x001f. test failure also asserts either the lbfa (loopback fail a) bit 5 or lbfb (loopback fail b) bit 4 in the built-in test word register, 0x0014. at rt loopback test completion, the host should clear self-test control register 0x0028, and then reset the test input pin to logic 0. HI-6130, hi-6131
holt integrated circuits 232 24.2.7. programmed bc-mode digital loopback testing (off-line) for any bc message block, off-line digital loopback self-test can be programmed. the test input pin should be logic 0, normal operational state. bc transmission onto the 1553 bus is inhibited for the message, but the digital transmit encoding and receive decoding signal paths can be checked. the bc instruction list in ram comprises a series of 2-word entries, an instruction op code word followed by a parameter word. while sequencing through the instruction list, the bc control logic fetches and executes conditional and unconditional instruction op codes referenced by the bc instruction list pointer 0x0034. for executable messages, the parameter word following the op code word contains the starting address of a message control/status block. as described in section 10.4. bus controller message control / status blocks on page 63 , each message control/ status block begins with a bc control word. when control word selftst bit 6 is set, off-line self-test is enabled, inhibiting transmission onto the 1553 bus. instead the output of the bus manchester ii serial encoder is routed directly to the decoder input for the bus selected by control word bit 7 (usebusa). a validity check is performed on the received replica of each transmitted word (sync, encoding, bit count and parity). as received, each word replica is stored in the loopback word location in the message control/status block. the data value for the fnal word received is also checked with the transmitted fnal word. if any word fails validity check (or if the fnal word has data mismatch) test logic sets the lbe (loopback error) bit 8 in the block status word. after message processing, off-line self-test success or failure can be determined by reading the received loopback word (stored in the message control/status block if bc is using 16-bit time base) or by reading the lbe (loopback error) bit 8 in the block status word. (note: if the bc is using 32-bit time base, the fnal received loopback word in the loopback word location is overwritten at the end of message post-processing when time tag bits 31:16 are written there.) the badmsg bc condition code 0xc is updated based on the outcome of the off-line selftst loopback message. badmsg is set to logic 1 for loopback test error. this permits conditional execution, including jumps or subroutine calls, based on the outcome of the message having selftst asserted in its control word. the badmsg condition code is also set for format error or no response error, but is not affected by a status set condition. for non-broadcast commands using off-line selftst loopback, no response error always occurs since the bc message processor expects an rt response. since bc bus transmission is inhibited, off-line selftst loopback should use broadcast commands. this avoids badmsg condition codes caused by no response error. 24.2.8. continuous bc-mode analog loopback testing (on-line) the bc performs continuous analog loopback on all bus controller transmissions when executing normal message control/status blocks having off-line selftst bit = 0 in each control word. the test input pin is logic 0, normal operational state. for each manchester ii word transmitted by the bc, a validity check is performed on the received replica, checking sync, encoding, bit count and parity. in the message control/status block, each received word replica is stored in the loopback word location when decoded, overwriting the previous word stored there. the data value for the fnal bc word received is also checked for data value. if any word fails validity check (or if the fnal word has data mismatch) test logic sets the lbe (loopback error) bit 8 in the block status word. (note: if the bc is using 32-bit time base, the fnal word replica in the loopback word location is overwritten at the end of message post-processing when time tag bits 31:16 are written there.) the badmsg bc condition code 0xc is updated based on the outcome of continuous bc-mode analog loopback checking. the badmsg condition code is set for loopback error, format error or no response error, but is not affected by a status set condition. bc analog loopback failure also sets lbe loopback error bit 8 in the block status word. HI-6130, hi-6131
holt integrated circuits 233 25. host interface 25.1. HI-6130 host bus interface the HI-6130 uses a parallel bus interface for communications with the host. host interface to registers and ram is enabled through the chip enable ( ce ) pin, and accessed via 16-bit data bus and several host-originated control signals described below. timing is identical for register operations and ram operations via the host bus interface, but read and write operations have different signal timing. the HI-6130 parallel host bus interface is capable of faster communication than the hi-6131 serial peripheral interface. depending on the chosen microprocessor family, the processors hardware bus interface may be described as an external bus interface, memory interface or may have a different name. the user can also implement a software controlled bit-banged interface to the HI-6130, at the cost of substantially slower ram and register read/write times. the bus interface is compatible with the two prevalent bus control signal methods: intel style interface, characterized by separate strobes for read and write operations ( oe and we ), and motorola style interface, characterized by a single read/write strobe ( str ) and a data direction signal (r/ w ). bus control style is selected using the btype con - fguration pin, which sets the function of two other input pins to serve as either oe and we , or str and r/ w . the bwid confguration pin selects either 8- or 16-bit bus widths. when the bwid pin is connected to ground, 8-bit mode is selected; two bytes are sequentially transferred for each 16-bit word operation. in 8-bit mode only, the bendi confguration pin selects bus endianness. this is the system attribute that indicates whether integers are represented with the most signifcant byte stored at the lowest address (big endian) or at the highest address (little endian). internal device storage is big endian. for processor compatibility, the bendi pin sets the order for byte accesses when the host bus is confgured for 8-bit width, that is, when bwid equals 0. when bendi is low, little endian is chosen; the low order byte (bits 7:0) is transacted before the high order byte (bits 15:8). when bendi is high, big endian is cho - sen and the high order byte is transacted on the host bus before the low order byte. in 8-bit mode, all transacted data uses bus data bits 7:0 and bus data bits 15:8 are not used. further, bus address bit a0 ( lb ) always equals 0 during the frst byte read/write access, and equals 1 during the second byte access when the bwid pin is connected high or left unconnected, 16-bit bus width is used. for 16-bit bus operation, the a0 ( lb ) address pin is not used and the bendi input pin is dont care. 25.1.1. bus wait states and data prefetch the HI-6130 has a wait output pin that tells the host to add wait states when additional access time is needed during bus read cycles. for compatibility with different host processors, the state of the wpol input pin sets the wait output as active high or active low. the wait output can be ignored when the host processor read cycle time is always slow enough to work with the HI-6130 bus. when using fast host processors, cycle time is sometimes slowed down by confguring the processor to add one or more wait states during every read or write cycle, but slow-down affects all cycles, even when unnecessary. data prefetch is a technique used by the HI-6130 to speed up host multi-word read access to registers or ram by eliminating wait states. prefetching occurs when HI-6130 logic requests data before it is actually needed. because register or ram locations are often read sequentially, performance improves when data is prefetched in address se - quence order. for every host read cycle, the device frst reads the addressed location, then prefetches the following address, to speed up access in the likely event that the following word will be read next. for the HI-6130, wait is always asserted for the frst word fetched in any read sequence. the frst read cycle has a long access time because there is no prefetch. this may be the frst byte read in 8-bit mode, or the frst word read in 16-bit mode. after each word (or byte) is fetched for a read operation, the next word (or byte) is prefetched to speed-up the read cycle time when sequential address read sequences occur. after the frst word read, the following words read in sequence are accessed without wait, resulting in faster overall multi-word read timing. as long as bytes or words are read in address order, additional wait states are unnecessary. data prefetch during read cycles is blocked when the next ram address is a control word in the descriptor table. the HI-6130, hi-6131
holt integrated circuits 234 table base address (set by the value in register 0x0005) and every fourth word thereafter is a control word. this con - sists of table addresses having these address offsets from the table start address of 0, 4, 8, 0xc 0x1f8 and 0x1fc. if allowed, prefetch (like any other read) would reset the control word dbac status bit, so prefetch is disallowed in this range. thus for HI-6130, multi-word sequential read sequences will assert wait every fourth word when reading ram within the 512-word descriptor table address range. for fastest read access under all conditions, the user can set host processor bus timing (by adjusting processor wait states for the chip select assigned to the HI-6130) to match the faster read cycle time for prefetched data, while the HI-6130 wait output adds one or more additional wait states for the slower initial read cycle. timing diagrams for bus read and write operations are shown in section 27 . separate diagrams show intel style and motorola style control interfaces. 25.2. hi-6131 serial peripheral interface in the hi-6131, internal ram and registers occupy a 32k x 16 address space. the lowest 80 addresses access registers and the remaining addresses access ram locations. timing is identical for register operations and ram operations via the serial interface, and read and write operations have likewise identical timing. 25.2.1. serial peripheral interface (spi) basics the hi-6131 uses an spi synchronous serial interface for host access to registers and ram. host serial communication is enabled through the chip enable (ce) pin, and is accessed via a three-wire interface consisting of serial data input (si) from the host, serial data output (so) to the host and serial clock (sck). all programming cycles are completely self-timed, and no erase cycle is required before write. the spi (serial peripheral interface) protocol specifes master and slave operation; the hi-6131 operates as an spi slave. the spi protocol defnes two parameters, cpol (clock polarity) and cpha (clock phase). the possible cpol-cpha combinations defne four possible spi modes. without describing details of the spi modes, the hi- 6131 operates in the two modes where input data for each device (master and slave) is clocked on the rising edge of sck, and output data for each device changes on the falling edge. these are known as spi mode 0 (cpha = 0, cpol = 0) and spi mode 3 (cpha = 1, cpol = 1). be sure to set the host spi logic for one of these modes. the difference between spi modes 0 and 3 is the idle state for the sck signal, which is logic 0 for mode 0 state and logic 1 for mode 3 state (see figure 26 ). there is no confguration setting in the hi-6131 to select spi mode 0 or mode 3 because compatibility is automatic. beyond this point, the hi-6131 data sheet only shows the spi mode 0 sck signal in timing diagrams. the spi protocol transfers serial data as 8-bit bytes. once ce chip enable is asserted, the next 8 rising edges on sck latch input data into the master and slave devices, starting with each bytes most-signifcant bit. the hi-6131 spi can be clocked at 20 mhz. HI-6130, hi-6131
holt integrated circuits 235 msb lsb msb lsb high z high z 01234567 ce so si sck (spi mode 3) 01234567 sck (spi mode 0) figure 26. generalized single-byte transfer using spi protocol. sck is shown for spi modes 0 and 3 multiple bytes may be transferred when the host holds ce low after the frst byte transferred, and continues to clock sck in multiples of 8 clocks. a rising edge on ce chip enable terminates the serial transfer and reinitializes the hi- 6131 spi for the next transfer. if ce goes high before a full byte is clocked by sck, the incomplete byte clocked into the device si pin is discarded. two byte transfers are needed for spi exchange of 16- bit register values or ram data. big endian byte order is used for spi data transfers. the high order byte (bits 15:8) is transferred before the low order byte (bits 7:0). in the general case, both master and slave simultaneously send and receive serial data (full duplex) per figure 26 . however the hi-6131 operates half duplex, maintaining high impedance on the so output, except when actually trans - mitting serial data. when the hi-6131 is sending data on so during read operations, activity on its si input is ignored. figure 27 and figure 28 show actual behavior for the hi-6131 so output. 25.2.2. hi-6131 spi commands for the hi-6131, each spi read or write operation begins with an 8-bit command byte transferred from the host to the device after assertion of ce. since hi-6131 command byte reception is half-duplex, the host discards the dummy byte it receives while serially transmitting the command byte. the hi-6131 spi command set uses the most signifcant command bit to specify whether the command is read or write. the command byte msb is zero for read commands, and one for write commands. 25.2.3. fast-access commands for registers 0-15 the spi command set includes directly-addressed read commands for registers 0 through 15. the 8-bit pattern for these read commands has the general form 0-0-r-r-r-r-0-0 where rrrr is the 4-bit register address. these fast-access read commands appear in table 24 . 25.2.4. fast-access write commands for registers 0-63 the spi command set includes directly-addressed write commands for registers 0 through 63. the 8-bit pattern for these read commands has the general form 1-0-r-r-r-r-r-r HI-6130, hi-6131
holt integrated circuits 236 where rrrrrr is the 6-bit register address. the fast-access write commands appear in table 24 . figure 27 and figure 28 show read and write timing as it appears for fast-access register operations. the command byte is immediately followed by two data bytes comprising the 16-bit data word read or written. for a register read or write, ce is negated after the 2-byte data word is transferred. 25.2.5. indirect addressing of ram and registers refer to the hi-6131 spi command set shown in table 25 . all spi commands other than fast-access use a memory address pointer register to indicate the starting address for read or write transactions. four memory address point - ers reside at register addresses 0x000b through 0x000e. just one memory address pointer (map) is active (enabled) at any time. the active memory address pointer is selected by writing the mapsel bits 11-10 in the master confguration register. or use the spi instruction op codes 0xd8, 0xd9, 0xda or 0xdb which enable map registers 0x000b, 0x000c, 0x000d or 0x000e respectively, by automatically writing mapsel bits 11-10 in the master confguration register. the active memory address pointer must be initialized before any read or write operation, other than fast-access. to write the active map register, use a fast-access write op code, followed by the desired 16-bit memory address: ? writing map register 0x000b uses spi op code 0x8b followed by 16-bit address. ? writing map register 0x000c uses spi op code 0x8c followed by 16-bit address ? writing map register 0x000d uses spi op code 0x8d followed by 16-bit address. ? writing map register 0x000e uses spi op code 0x8e followed by 16-bit address. to read the active map register, use a fast-access write op code. the current map 16-bit value is clocked out in the next 16 sequential sck clock cycles: ? reading map register 0x000b uses spi op code 0x2c ? reading map register 0x000c uses spi op code 0x30 ? reading map register 0x000d uses spi op code 0x34 ? reading map register 0x000e uses spi op code 0x38 while spi command op codes are always 8 bits, transacted addresses and register or memory data are always 16- bit words, transferred by the spi as two sequential bytes. after a 2-byte read/write completion, the active memory address pointer automatically increments to the following register address. the host can extend the read or write operation to the next register address by continuing to hold ce low while clocking sck 16 additional times. this auto- increment feature can be used to access one or more sequential register addresses above the command address. auto-increment applies (ranging to the top of the address space) as long as sck continues to be clocked under continuous ce assertion. caution: when the primary address pointer is used for auto-incrementing multi-word read/ write and reaches the top of the address range (0x7fff) the next increment rolls over the map value to 0x0000. the host should avoid this situation. HI-6130, hi-6131
holt integrated circuits 237 ce so si sck spi mode 0 msb lsb 0 12 3 4 5 67 high z high z 0 12 3 4 5 67 0 12 3 4 5 67 msb lsb msb lsb data byte 0 command byte host may continue to assert ce here to read sequential word(s). each word needs 16 sck clocks. data byte 1 figure 27. single-word (2-byte) read from ram or a register lsb 0 12 3 4 5 67 0 12 3 4 5 67 0 12 3 4 5 67 msb lsb ms b lsb host may continue to assert ce here to write sequential word(s). each word needs 16 sck clocks. ce so si sck spi mode 0 msb high z command byte data byte 0 data byte 1 figure 28. single-word (2-byte) write to ram or a register HI-6130, hi-6131
holt integrated circuits 238 three single-byte spi commands modify the value in the active memory address pointer, selected by mapsel bits 11-10 in the master confguration register: command address pointer operation 0xd0 increment enabled memory address pointer value 0xd2 add 2 to enabled memory address pointer value 0xd4 add 4 to enabled memory address pointer value the add 4 command may be useful when sequentially accessing the same word (for example, the control word) in a series of 4-word descriptor table entries. the add 2 command might be useful for reading the interrupt log buf - fer, comprised of 2-word log entries. in both cases, the add command would be probably followed by read command 0x40 to read the location addressed by the current pointer value. similarly, write command 0xc0 writes the location addressed by the current pointer value. two command bytes cannot be chained; the host spi slave select ce must be negated after the add command, then reasserted for the following read or write command. the active memory address pointer is not affected by fast-access read/writes to the low register addresses because fast-access spi commands use a separate, internal pointer not directly accessible to the host. two single-byte spi commands use the current value of the enabled memory address pointer without frst loading or otherwise modifying it: command read operation 0x40 read location addressed by enabled memory address pointer command write operation 0xc0 write location addressed by enabled memory address pointer either of these commands can be used to read or write a single location, or may be used to start a multi-word read or write that uses the map pointers auto-increment feature. one single-byte spi command increment the current value of the enabled memory address pointer, then performs a write: command write operation 0xc8 add 1 to enabled memory address pointer then write addressed location 25.2.6. data prefetch for spi read cycles data prefetch is a technique used by the hi-6131 to speed up host multi-word read access to registers or ram. prefetching occurs when hi-6131 logic accesses data before it is actually needed. because register or ram loca - tions are often read sequentially, performance improves when data is prefetched in address sequence order. for any spi read cycle, the hi-6131 frst fetches the addressed location, then increments the memory address pointer and prefetches the following address, to speed up access in the likely event that the following word will be read next. for the hi-6131, read cycle prefetch allows the spi host to read sequential locations back-to-back, continuing as long as the host asserts chip select and provides spi clock. this is described as the memory address pointer auto-increment feature. HI-6130, hi-6131
holt integrated circuits 239 there is an exception: read cycle prefetch is blocked when the next ram address is a control word in the rt1 or rt2 descriptor table. if allowed, pre-fetch (like any other read) resets the control word dbac status bit. to preserve dbac status bit function, prefetch is disabled when reading control words within descriptor table address range. the table base address (set by the value in register 0x0019 for rt1 or register 0x0022 for rt2) and every fourth word thereafter is a control word. this consists of table addresses having these offsets from the table start address: 0, 4, 8, 0xc through and including 0x1f8 and 0x1fc. see further information in section 25.2.8 . these two commands can be used to read or write a single location, or may be used to start a multi-word read or write that uses the pointers auto-increment feature. 25.2.7. special purpose commands several other hi-6131 spi commands load or otherwise modify the active memory address pointer before initiating a read or write process. these commands were tailored to the specifc needs of hi-6131 remote terminal host software. using a single-byte spi command, the active memory address pointer can be directly loaded with the memory ad - dress for the rt1 or rt2 descriptor table control word corresponding to the last completed mil-std-1553 command. the control word is then read. command read operation 0x48 copy rt1 current control word address register 3 into the enabled memory address pointer. read the location addressed by the new pointer value. 0x50 copy rt2 current control word address register 5 into the enabled memory address pointer. read the location addressed by the new pointer value. this command can be used to read just the current rt1 or rt2 control word, or may be used to start a multi-word read because memory pointer auto-increment occurs after the control word is read. six single-byte spi commands add an offset to the current address pointer value, then read the addressed memory location; the read value is then written to the address pointer register 15. the new pointer value is used to start a read or write operation: command read operation 0x68 read the location addressed by the enabled memory address pointer. write the value just read into the memory address pointer. then read. 0x70 add 1 to the enabled memory address pointer. read value at newly addressed location and write it into the memory address pointer. then read. 0x78 add 2 to the enabled memory address pointer. read value at newly addressed location and write it into the memory address pointer. then read. HI-6130, hi-6131
holt integrated circuits 240 command write operation 0xe8 read the location addressed by the enabled memory address pointer. write the value just read into the memory address pointer. then write. 0xf0 add 1 to the enabled memory address pointer. read value at newly addressed location and write it into the memory address pointer. then write. 0xf8 add 2 to the enabled memory address pointer. read value at newly addressed location and write it into the memory address pointer. then write. primary use occurs when an rt1 or rt2 descriptor table control word was just read. for example, the last op code performed was 0x48, reading the rt1 control word for the last command. after reading the control word, the enabled memory address pointer automatically incremented. the host can examine fag bits contained in the just-read control word to determine the applicable data buffer (e.g., data buffer a, data buffer b or the broadcast data buffer) then directly service that buffer using these op codes; the three data buffer pointers occur in the three words following the initially read control word. these six commands can be used to read or write a single location, or may be used to start a multi-word read or write that uses the pointers auto-increment feature. when some or all subaddress or mode commands are not programmed to trigger host interrupts, a different single- byte spi command may be useful if polling the rt1 or rt2 descriptor table for message activity. in this situation, the host may poll a series of descriptor table control words looking for instances where the dbac activity bit is set. the dbac (descriptor block accessed) fag is set in the control word each time the corresponding command is com - pleted. the process of reading the control word automatically resets the registers dbac bit so the host can detect activity the next time the dbac fag is set by the device. since rt1 or rt2 descriptor table control words are spaced four words apart, this command is useful when polling a series of descriptor table control words: command read operation 0x60 read addressed location then add 4 to pointer primary use occurs when the address pointer initially points to the frst descriptor table control word in a series of control words to be polled (every fourth word). after 8 sck clocks for the spi command, each instance of this command reads a single location using 16 sck clocks. if cs remains low after 24 clocks and sck continues, a multi-word read begins, using the address pointers auto- increment feature. the second word read is at (control word address + 4), the next control word in the table. another single-byte spi command is useful when servicing interrupts. when enabled interrupts occur, two words are written to the circular 64-word interrupt log buffer, and the interrupt log address register 0x000a is updated to show the storage address where interrupt information words will be stored for the next occurring interrupt. buffer starting address is 0x0180 and ending address is 0x01bf. because two words are written to the buffer for each interrupt, the interrupt log address register always contains an even value in the range of 0x0180 to 0x01be. when servicing an interrupt that just occurred, the host wants timely information on that interrupt. an spi command is provided to simplify interrupt handling: HI-6130, hi-6131
holt integrated circuits 241 command read operation 0x58 write enabled memory address pointer with the current bit 8:0 address value in interrupt log address register minus 1. (see note.) if address bits 8:0 equal 0x0180, then 0x1bf is written into mem - ory address pointer. then read the new - ly-addressed ram location, containing the last-written interrupt address word. then decrement the memory address pointer, which then addresses the cor - responding interrupt information word note : bits 15:9 in the interrupt log address register contain the interrupt count since the log address register was last read. these bits are not written to the memory address pointer. this command can be used to read a single location (the last-written interrupt address word), or may be used to start a multi-word read in which the memory address pointer automatically decrements after each word is read, read - ing words stored in the interrupt log buffer, in last in first out order. this is the only spi op code that decrements the memory address pointer for multi-word operations. repeated memory pointer decrements will wrap around the 0x0180 to 0x01bf interrupt log buffer boundary. 25.2.8. rt descriptor table prefetch exceptions for the spi-interface hi-6131, the enabled memory address pointer (register 0x000f) contains the address for each new word read by the host. when starting a read access, the host usually writes the enabled memory address pointer with the address for the frst word to read. the host then uses an spi op code to initiate the read process. after the addressed word is transferred by spi to the host, the hi-6131 continues to read and transmit words from sequential ram memory addresses, as long as the host continuously asserts chip select while providing sck serial clock pulses. after fetching each new word, the device increments the memory address pointer and prefetches the data contained in the newly addressed location. the next word is prefetched even when the host does not ultimately read the follow - ing address. for hi-6131, sequential reads from the rt1 or rt2 descriptor table that rely on map auto-increment will stop advancing when the next address contains a rt descriptor table control word. properly designed spi transfers overcome this behavior. using spi command op codes, the hi-6131 host must consider prefetch and pointer behavior when reading data from the descriptor table. applied outside the rt descriptor table, the following spi sequence would read data from six successive memory addresses. but below, applied within the table, the sequence gets stuck at the fourth word read. below we assume the rt1 descriptor table starts at default base address, 0x0400. the host frst uses spi op codes 0xd8 and 0x8b to enable memory address pointer 0x000b then write the table start address 0x0400 into it. the se - quence then uses op code 0x40 (and map auto-increment) to read the frst map-addressed location and successive locations. notice : there is no map auto-increment or data prefetch when map equals 0x0403, so the fnal two read cycles re - peat the previous read value and address. from from host hi-6131 comment ===== ======= ========================================== 0xd8 ---- spi op enables memory address pointer (map) 0x000b. 0x8b ---- spi op code writes memory address pointer (map). 0x0400 ---- rt1 descriptor table start address written to map. HI-6130, hi-6131
holt integrated circuits 242 0x40 ---- spi op code to read location addressed by map ---- data from 0x0400 (sck continues afterward) ---- data from 0x0401 (sck continues afterward) ---- data from 0x0402 (sck continues afterward) ---- data from 0x0403 (sck continues afterward, control word next) ---- data from 0x0403 (sck continues afterward, control word next) ---- data from 0x0403 (sck stops and /cs is then negated) using a different spi op code sequence, the host can read the entire rt1 descriptor table without getting stuck at the frst control word read by the multi-word transfer using op code 0x40: from from host hi-6131 comment ===== ======= ========================================== 0xd8 ---- spi op enables memory address pointer (map) 0x000b. 0x8b ---- op code writes memory address pointer (map) 0x03ff ---- decremented table start addr 0x0400 - 1 written to map 0xd0 ---- op code increments enabled map 0x40 ---- op code reads map-addressed location ---- data from 0x0400 (sck continues afterward) ---- data from 0x0401 (sck continues afterward) ---- data from 0x0402 (sck continues afterward) ---- data from 0x0403 (sck stops and /cs is negated) 0xd0 ---- op code increments enabled map 0x40 ---- op code reads map-addressed location ---- data from 0x0404 (sck continues afterward) ---- data from 0x0405 (sck continues afterward) ---- data from 0x0406 (sck continues afterward) ---- data from 0x0407 (sck stops and /cs is negated) 0xd0 ---- op code increments enabled map 0x40 ---- op code reads map-addressed location ---- data from 0x0408 (sck continues afterward) ---- data from 0x0409 (sck continues afterward) ---- data from 0x040a (sck continues afterward) ---- data from 0x040b (sck stops and /cs is negated) the host may repeat this sequence until the entire rt1 descriptor table is read. the repeating read process is not shown, but the sequence could end like this, stopping at the upper table boundary 0xd0 ---- op code increments enabled map 0x40 ---- op code reads map-addressed location ---- data from 0x05fc (sck continues afterward) ---- data from 0x05fd (sck continues afterward) ---- data from 0x05fe (sck continues afterward) ---- data from 0x05ff (sck stops and /cs is negated) table ends in most situations, the repeating op code block (0xd0 with 8 sck clocks and op code 0x40 with 72 sck clocks) would be implemented as a loop, rather than straight-line code. a total of 128 loop repetitions would be required to read the rt descriptor table from start to fnish. HI-6130, hi-6131
holt integrated circuits 243 table 24. fast-access spi commands for lower registers op code bits 5:2 convey the 4-bit register read address. command bits 5:0 convey the 6-bit register write address. command bits 7 6 5 4 3 2 1 0 hex byte fast-access read command bits 7 6 5 4 3 2 1 0 hex byte fast-access write 0 0 0 0 0 0 0 0 0x00 read register 0 1 0 0 0 0 0 0 0 0x80 write register 0 0 0 0 0 0 1 0 0 0x04 read register 1 1 0 0 0 0 0 0 1 0x81 write register 1 0 0 0 0 1 0 0 0 0x08 read register 2 1 0 0 0 0 0 1 0 0x82 write register 2 0 0 0 0 1 1 0 0 0x0c read register 3 1 0 0 0 0 0 1 1 0x83 write register 3 0 0 0 1 0 0 0 0 0x10 read register 4 1 0 0 0 0 1 0 0 0x84 write register 4 0 0 0 1 0 1 0 0 0x14 read register 5 1 0 0 0 0 1 0 1 0x85 write register 5 0 0 0 1 1 0 0 0 0x18 read register 6 1 0 0 0 0 1 1 0 0x86 write register 6 0 0 0 1 1 1 0 0 0x1c read register 7 1 0 0 0 0 1 1 1 0x87 write register 7 0 0 1 0 0 0 0 0 0x20 read register 8 1 0 0 0 1 0 0 0 0x88 write register 8 0 0 1 0 0 1 0 0 0x24 read register 9 1 0 0 0 1 0 0 1 0x89 write register 9 0 0 1 0 1 0 0 0 0x28 read register 10 1 0 0 0 1 0 1 0 0x8a write register 10 0 0 1 0 1 1 0 0 0x2c read register 11 1 0 0 0 1 0 1 1 0x8b write register 11 0 0 1 1 0 0 0 0 0x30 read register 12 1 0 0 0 1 1 0 0 0x8c write register 12 0 0 1 1 0 1 0 0 0x34 read register 13 1 0 0 0 1 1 0 1 0x8d write register 13 0 0 1 1 1 0 0 0 0x38 read register 14 1 0 0 0 1 1 1 0 0x8e write register 14 0 0 1 1 1 1 0 0 0x3c read register 15 1 0 0 0 1 1 1 1 0x8f write register 15 decimal 15 is end of read address range 1 0 0 1 0 0 0 0 0x90 write register 16 1 0 0 1 0 0 0 1 0x91 write register 17 1 0 0 1 0 0 1 0 0x92 write register 18 1 0 0 1 0 0 1 1 0x93 write register 19 1 0 0 1 0 1 0 0 0x94 write register 20 1 0 0 1 0 1 0 1 0x95 write register 21 and so on, to 63 decimal . . 1 0 1 1 1 1 0 1 0xbd write register 61 1 0 1 1 1 1 1 0 0xbe write register 62 1 0 1 1 1 1 1 1 0xbf write register 63 decimal 63 is end of write address range HI-6130, hi-6131
holt integrated circuits 244 table 25. spi commands using memory address pointer hex byte read or write read select / enable a memory address pointer 0xd8 ------- enable memory address pointer at register 0x000b 0xd9 ------- enable memory address pointer at register 0x000c 0xda ------- enable memory address pointer at register 0x000d 0xdb ------- enable memory address pointer at register 0x000e memory address pointer operations (no data is written or read) 0xd0 ------- add 1 to the current value of the enabled memory address pointer 0xd2 ------- add 2 to the current value of the enabled memory address pointer 0xd4 ------- add 4 to the current value of the enabled memory address pointer read / write ram or register location using current address pointer value 0x40 r read location addressed by the current value of the enabled memory address pointer 0xc0 w write location addressed by the current value of the enabled memory address pointer increment address pointer then write addressed ram or register location 0xc8 w write addressed location after incrementing the enabled memory address pointer special purpose commands 0x48 r copy rt1 current control word address (register 3) to enabled memory address pointer, then read the location addressed by the new pointer value (read the current control word for rt1) 0x50 r copy rt2 current control word address (register 5) to enabled memory address pointer, then read the location addressed by the new pointer value (read the current control word for rt2) 0x68 r add 0 to the current value of the enabled memory address pointer. then . . . 0x70 r add 1 to the current value of the enabled memory address pointer. then . . . 0x78 r add 2 to the current value of the enabled memory address pointer. then copy value from newly addressed location to the enabled memory address pointer then read newly addressed location. 0xe8 w add 0 to the current value of the enabled memory address pointer. then . . . 0xf0 w add 1 to the current value of the enabled memory address pointer. then . . . 0xf8 w add 2 to the current value of the enabled memory address pointer. then copy value from newly addressed location to the enabled memory address pointer then write newly addressed location. 0x60 r read then add 4 to the current value of the enabled memory address pointer. 0x58 r write storage address of last-written interrupt address word to the enabled memory address pointer, then read the interrupt address word from the interrupt log buffer. decrement memory address pointer after read operation HI-6130, hi-6131
holt integrated circuits 245 26. appendix: rt messages responses, options & exceptions circumstances for received message terminal response to received command bits updated in descriptor control word bits updated in data buffer msg info word interrupt options invalid command word (manchester, parity or bit count error) no terminal response, the message is ignored. no status word change. no change no message info word is written none any valid command to rt31 (broadcast). when the bcstinv bit in the rt confguration register equals 1. no terminal response, the message is ignored. no status word change. (broadcast commands are rendered invalid.) no change no message info word is written none rt address parity error based on rta and rtap bits in the operational status register for commands to the rts own address or to broadcast address rt31: no terminal response, message is ignored. no status word change. no change no message info word is written rtapf (not optional) any valid non-mode (subaddress 1-30) transmit command to rt31 (undefned broadcast transmit). no terminal response, set message error (me) and bcr status bits. dbac bit set. dpb bit toggles. bcast bit set. merr bit set. busid bit updated. iwa ibr (ixeqz) any valid non-mode (subaddress 1-30) transmit command except for rt31. the corresponding bit in the illegalization table equals 0.* normal status word response (clear status). data words for transmit are read from the ram data buffer assigned by the descriptor table entry for the transmit subaddress. dbac bit set. dpb bit toggles. bcast bit reset. normal cs update: busid bit updated. merr bit reset. ilcmd bit reset. rtrt bit updated. (other error bits reset). iwa ibr (ixeqz) any valid non-mode (subaddress 1-30) transmit command except for rt31. the corresponding bit in the illegalization table equals 1. ** assert message error (me) status, then transmit me status word without following data words. dbac bit set. dpb bit toggles. bcast bit reset. ilcmd bit set. busid bit updated. merr bit set. rtrt bit updated. (other error bits reset). ilcmd iwa any valid non-mode (subaddress 1-30) receive command. the corresponding bit in the illegalization table equals 0. * normal status word response (clear status). after message completion, the data words received are stored in the data buffer ram location assigned by the descriptor table entry for the receive subaddress. dbac bit set. dpb bit toggles. bcast bit reset. normal update: busid bit updated. merr bit reset. ilcmd bit reset. rtrt bit updated. (other error bits reset). iwa ibr (ixeqz) * terminal is using illegal command detection and command is legal or terminal is not using illegal command detection and command may be legal or illegal (in form response). ** terminal is using illegal command detection and command is illegal. HI-6130, hi-6131
holt integrated circuits 246 circumstances for received message terminal response to received command bits updated in descriptor control word bits updated in data buffer msg info word interrupt options any valid non-mode (subaddress 1-30) receive command. the corresponding bit in the illegalization table equals 1. ** assert message error (me) status and set bcr if broadcast. any received data words are ignored and are not saved. when data reception stops, transmit status word. dbac bit set. dpb bit toggles. bcast bit updated. ilcmd bit set. busid bit updated. merr bit set. rtrt bit updated. (other error bits reset) ilcmd iwa ibr (ixeqz) valid receive command followed by invalid data word (manchester, parity or bit count error). no terminal response. set message error (me) status. if broadcast (rt31), also set the bcr status bit. dbac bit set. bcast bit updated. dpb bit toggles. merr bit set. busid bit updated. iwderr bit set. ilcmd bit reset. rtrt bit updated (other error bits reset). merr iwa ibr valid receive command followed by one or more good data words, then a data word having command sync. no terminal response. set message error (me) status. if broadcast (rt31), also set the bcr status bit. dbac bit set. bcast bit updated. dpb bit toggles. merr bit set. busid bit updated. synerr bit set. ilcmd bit reset. (other error bits reset). merr iwa ibr any valid command followed by wrong number of data words (too few or too many words) no terminal response. set message error (me) status. if broadcast (rt31), also set the bcr status bit. dbac bit set. bcast bit updated. dpb bit toggles. merr bit set. busid bit updated. set wcterr (too few) or gaperr (too many). ilcmd bit reset. rtrt bit updated. (other error bits reset). merr iwa ibr rt-rt where cw1 is a valid non-mode receive command. cw2 is a non-mode transmit command valid for different rt. (normal rt-rt receive message) normal status word response (clear status). if rt-rt command word 1 is broadcast (rt31) set the bcr status bit. dbac bit set. bcast bit updated. dpb bit toggles. normal cs update: busid bit updated. rtrt bit set. rtcwerr bit reset. ilcmd bit reset. (all error bits reset). iwa ibr (ixeqz) rt-rt where cw1 is a valid non-mode receive command. transmit command cw2 has an error: t/ r bit = 0, or cw2 subaddress equals 0 or 31 (mode code), or cw2 has same rt address as cw1. no terminal response. set message error (me) status. if rt-rt command word 1 is broadcast (rt31) also set the bcr status bit, dbac bit set. bcast bit updated. dpb bit toggles. merr bit set. busid bit updated. rtrt bit set. rtrtcwerr bit set. ilcmd bit reset. (other error bits reset). merr iwa ibr HI-6130, hi-6131
holt integrated circuits 247 circumstances for received message terminal response to received command bits updated in descriptor control word bits updated in data buffer msg info word interrupt options rt-rt where cw1 is a valid non-mode receive command. cw2 is valid for different rt but transmitting rt does not respond in time. no terminal response. set message error (me) status. if rt-rt command word 1 is broadcast (rt31), also set the bcr status bit. dbac bit set. bcast bit updated dpb bit toggles. merr bit set. busid bit updated. rtrt bit set. tmoerr bit set. ilcmd bit reset. (other error bits reset). merr iwa ibr rt-rt receive command (cw1 is valid). the transmitting rt response has one of these errors: invalid word (manchester, (sync, bit count, parity or word count error). also includes transmitting rt response with message error or busy status followed by no data words. no terminal response. set message error (me) status. if rt-rt command word 1 is broadcast (rt31) also set the bcr status bit. dbac bit set. bcast bit reset. dpb bit toggles. merr bit set. buisid bit reset. rtrt bit set. iwderr bit set, or wcterr bit set for tx rt busy case. ilcmd bit reset. (other error bits reset). merr iwa ibr rt-rt command where cw2 is a valid non-mode (subaddress 1-30) transmit command. cw1 is a non-mode receive command for rt31. (normal broadcast rt-rt transmit) normal status word response. clear status is transmitted with the commanded number of data words. data words for transmit are read from the ram data buffer assigned in the descriptor table entry for the transmit subaddress. dbac bit set. bcast bit reset. dpb bit toggles. normal cs update: busid bit updated. merr bit reset. ilcmd bit reset. rtrt bit set. (all error bits reset). iwa (ixeqz) valid mode code command to rt31 (broadcast). the bcstinv bit in the rt confguration register equals 1. no terminal response, the message is ignored. no status word change. no change no message info word is written none valid undefned mode code command. the umcinv bit in the rt confguration register equals 1. no terminal response, the message is ignored. no status word change. note: this only applies for the undefned mode codes: mc0 to mc15 with t/ r = 0 mc16,18 & 19 with t/ r = 0 mc17,20 & 21 with t/ r = 1 no change no message info word is written none HI-6130, hi-6131
holt integrated circuits 248 circumstances for received message terminal response to received command bits updated in descriptor control word bits updated in data buffer msg info word interrupt options valid defned mode code command (including reserved mode code) not illegalized by illegalization table (table bit equals 0 *) if mc2 (transmit status) or mc18 (transmit last command) status word from last command is transmitted. if mc18, data word transmitted is read from an internal register. or if not mc2 or mc18, normal status word response. if broadcast, assert status word bcr bit. for mode codes 16-31 with t/ r bit = 1 which transmit a data word, the word for transmit is read from the mode command data table. and for all mode commands with mode data word (mode codes 16-31), the transmitted or received data word is written to commands descriptor word 4. dbac bit set. bcast bit updated. dpb bit toggles. normal cs update: busid bit updated. merr bit reset. ilcmd bit reset. rtrt bit reset. (all error bits reset.) iwa ibr (ixeqz) valid defned mode code command that is illegalized by the illegalizationtable (table bit equals 1 **) set message error (me) status. if not broadcast (rt31), transmit. status word without a following mode data word. if broadcast (rt31), also assert the bcr status bit. and for mode commands with a mode data word (mode codes 16-31), no updates are made to the mode command data table or to the commands word 4 in descriptor table. dbac bit set. bcast bit updated. dpb bit toggles. ilcmd bit set. busid bit updated. merr bit reset. rtrt bit reset. (other error bits reset.) ilcmd iwa ibr * terminal is using illegal command detection and command is legal or terminal is not using illegal command detection and command may be legal or illegal (in form response). ** terminal is using illegal command detection and command is illegal. HI-6130, hi-6131
holt integrated circuits 249 circumstances for received message terminal response to received command bits updated in descriptor control word bits updated in data buffer msg info word interrupt options valid undefned mode code command. the umcinv bit in the rt confguration register equals 0. if bit in illegalization table that corresponds to the undefned mode code command equals 1 ** set message error (me) status, if not broadcast (rt31), transmit status word without a following mode data word. if broadcast (rt31), also assert the bcr status bit. or if bit in illegalization table that corresponds to the undefned mode code command equals 0 * normal status word (clear status) response. if command was broadcast (rt31), assert the bcr status bit. and for mode codes 16-31 with t/ r bit = 1 which transmit a data word, the word for transmit is read from the mode command data table. and for all mode commands with mode data word (mode codes 16-31), the transmitted or received data word is written to commands descriptor word 4. dbac bit set. bcast bit updated. dpb bit toggles. dbac bit set. bcast bit updated. dpb bit toggles. ilcmd bit set. busid bit updated. merr bit reset. rtrt bit reset. (other error bits reset.) normal cs update: busid bit updated. merr bit reset. ilcmd bit reset. rtrt bit reset. (all error bits reset.) ilcmd iwa ibr iwa ibr (ixeqz) * terminal is using illegal command detection and command is legal or terminal is not using illegal command detection and command may be legal or illegal (in form response). ** terminal is using illegal command detection and command is illegal. HI-6130, hi-6131
holt integrated circuits 250 circumstances for received message terminal response to received command bits updated in descriptor control word bits updated in data buffer msg info word interrupt options valid receive command followed by invalid data word (manchester, parity or bit count error). no terminal response. set status word me bit, if broadcast, also set status word bcr bit. dbac bit set. bcast bit updated. dpb bit toggles. merr bit set. busid bit updated. iwderr bit set. ilcmd bit reset. rtrt bit updated. (other error bits reset.) merr iwa ibr superseded message: terminal receives an incomplete message interrupted by a gap of at least 3.5 us, followed by a new valid command on the same bus or on the other bus or terminal is transacting a transmit message on one bus and receives the start of a valid command on the other bus. terminal aborts processing for frst message and responds in full to the second (superseding) message. the status word bcr bit refects broadcast status for: the second command, unless second command is mc2 (transmit status) or mc18 (transmit last command). no change to superseded commands control word. for superseding commands control word: dbac bit set. bcast bit updated dpb bit toggles. no msg info word written for the superseded command. for superseding commands data buffer, a normal cs update: busid bit updated. merr bit reset. ilcmd bit reset. rtrt bit updated. (all error bits reset.) none for super - seded command iwa ibr (ixeqz) terminal is busy for a valid receive command either globally (busy bit set in status word bits register) or in response to a particular valid receive command (mkbusy bit set in the commands descriptor table control word.) busy bit is set in the 1553 status bits register. status word is transmitted, unless broadcast. if broadcast, the bcr bit in status word is also set. after message completion, data words received are stored in the data buffer assigned by the receive subaddress descriptor table entry. dbac bit set. bcast bit updated. dpb bit toggles. wasbsy bit set. busid bit updated. merr bit reset. ilcmd bit reset. rtrt bit updated. (all error bits reset.) iwa ibr terminal is busy for a valid transmit command either globally (busy bit set in status word bits register) or in response to a particular valid receive command (mkbusy bit set in the commands descriptor table control word.) busy bit is set in the 1553 status bits register. if not broadcast, status word is transmitted without data. if broadcast, the bcr bit in status word is also set. dbac bit set. bcast bit updated, (mode commands with t/ r = 1) dpb bit toggles wasbsy bit set. busid bit updated. merr bit reset. ilcmd bit reset. rtrt bit updated. (all error bits reset.) iwa ibr HI-6130, hi-6131
holt integrated circuits 251 circumstances for received message terminal response to received command bits updated in descriptor control word bits updated in data buffer msg info word interrupt options dynamic bus control (mc0): mode code command with mode code 00000 and t/ r bit equals 1 hi-6110 is not equipped to accept bus control duties. the host must initialize device to respond using either of the two following methods: the mode codes bit in illegalization table equals 0 * or the mode codes bit in illegalization table equals 1 ** rt is not using illegal command detection. respond in form: reset message error (me) status and transmit status word. or rt is using illegal command detectionand mode code is illegalized. set message error (me) status and transmit status word. dbac bit set. bcast bit reset. dpb bit toggles. dbac bit set. bcast bit reset. dpb bit toggles. normal cs update: busid bit updated. merr bit reset. ilcmd bit reset. rtrt bit reset. (all error bits reset.) ilcmd bit set. busid bit updated. merr bit reset. rtrt bit reset. (other error bits reset.) iwa ilcmd iwa mc0 exceptions: broadcast address rt31 (broadcast not allowed) no status word transmit. set the message error (me) and bcr status bits. dbac bit set. bcast bit set. dpb toggles. merr bit set. busid bit updated. ilcmd bit reset. rtrt bit reset. (other error bits reset.) merr iwa ibr mode code command word is followed by a contiguous data word no status word transmit. set the message error (me) status bit. dbac bit set. bcast bit reset. dpb bit toggles. merr bit set. wcterr bit set. busid bit updated. ilcmd, rtrt bits reset. (other error bits reset.) merr iwa invalid command word. or t/ r bit equals 0 and umcinv bit in the rt confguration register equals 1 *** no terminal response, the message is ignored. no status word change. (mc0 is not ndefned when t/ r bit equals 0) no change no message info word is written none * command is illegal but terminal is not using illegal command detection (in form response). ** command is illegal and terminal is using illegal command detection *** undefned mode command rendered invalid by umcinv option bit. command s bit in illegalization table is dont care. HI-6130, hi-6131
holt integrated circuits 252 circumstances for received message terminal response to received command bits updated in descriptor control word bits updated in data buffer msg info word interrupt options t/ r bit equals 0 and umcinv bit in the rt confguration register equals 0. illegalization table bit equals 0 * respond in form: reset message error (me) status and transmit status word. dbac bit set. bcast bit reset. dpb bit toggles. normal cs update: busid bit updated. merr bit reset. ilcmd bit reset. rtrt bit reset. (all error bits reset.) iwa ibr t/ r bit equals 0 and umcinv bit in the rt confguration register equals 0. illegalization table bit equals 1 ** set message error (me) status and transmit status word. dbac bit set. bcast bit reset. dpb bit toggles. ilcmd bit set. merr bit set. busid bit updated. rtrt bit reset. (other error bits reset.) ilcmd iwa ibr * command is illegal but terminal is not using illegal command detection (in form response). ** command is illegal and terminal is using illegal command detection HI-6130, hi-6131
holt integrated circuits 253 circumstances for received message terminal response to received command bits updated in descriptor control word bits updated in data buffer msg info word interrupt options synchronize without data (mc1): mode code command with mode code 00001 and t/ r bit equals 1 default response: reset message error (me) status then transmit status word. if broadcast, set the status word bcr bit and suppress status word transmit. reset the time tag counter to 0x0000. dbac bit set. bcast bit updated. dpb bit toggles. normal update: busid bit updated. merr bit reset. ilcmd bit reset. rtrt bit reset. (all error bits reset.) iwa ibr mc1 exceptions: invalid command word. or t/ r bit equals 0 and umcinv bit in the rt confguration register equals 1 *** no terminal response, the message is ignored. no status word change. (mode code is undefned when t/ r bit equals 0) no change no message info word is written none t/ r bit equals 0 and umcinv bit in the rt confguration register equals 0. the illegalization table bit equals 0 * respond in form: reset message error (me) status. if not broadcast, transmit status word. if broadcast, set the bcr status bit and suppress status response. the time tag counter is not reset. dbac bit set. bcast bit updated. dpb bit toggles. normal update: busid bit updated. merr bit reset. ilcmd bit reset. rtrt bit reset. (all error bits reset.) iwa ibr t/ r bit equals 0 and umcinv bit in the rt confguration register equals 0. the illegalization table bit equals 1 ** set message error (me) status. if not broadcast, transmit status word. if broadcast, also set status word bcr bit and suppress status response. the time tag counter is not reset. dbac bit set. bcast bit updated. dpb bit toggles. ilcmd bit set. merr bit set. busid bit updated. rtrt bit reset. (other error bits reset.) ilcmd iwa ibr mode code command word is followed by a contiguous data word no status word transmit. set the message error (me) status bit. dbac bit set. bcast bit updated. dpb bit toggles. merr bit set. wcterr bit set. busid bit updated. ilcmd bit reset. rtrt bit reset. (other error bits reset.) merr iwa * command is illegal but terminal is not using illegal command detection (in form response). ** command is illegal and terminal is using illegal command detection *** undefned mode command rendered invalid by umcinv option bit. command s bit in illegalization table is dont care. HI-6130, hi-6131
holt integrated circuits 254 circumstances for received message terminal response to received command bits updated in descriptor control word bits updated in data buffer msg info word interrupt options transmit status (mc2): mode code command with mode code 00010 and t/ r bit equals 1 no status word updates, transmit status from last valid command (assuming last command was not a transmit status or a transmit last command mode command. dbac bit set. bcast bit reset. dpb bit toggles. normal cs update: busid bit updated. merr bit reset. ilcmd bit reset. rtrt bit reset. (all error bits reset.) iwa mc2 exceptions: broadcast address rt31 (broadcast not allowed) no status word transmit. set the message error (me) and bcr status bits. dbac bit set. bcast bit set. dpb bit toggles. merr bit set. busid bit updated. ilcmd bit reset. rtrt bit reset. (other error bits reset.) merr iwa ibr invalid command word. or t/ r bit equals 0 and umcinv bit in the rt confguration register equals 1 *** no terminal response, the message is ignored. no status word change. (mode code is undefned when t/ r bit equals 0) no change no message info word is written none t/ r bit equals 0 and umcinv bit in the rt confguration register equals 0 the illegalization table bit equals 0 * respond in form: reset message error (me) status. if not broadcast, transmit status word. if broadcast, set the bcr status bit and suppress status response. time tag counter is not reset. dbac bit set. bcast bit updated. dpb bit toggles. normal cs update: busid bit updated. merr bit reset. ilcmd bit reset. rtrt bit reset. (all error bits reset.) iwa ibr t/ r bit equals 0 and umcinv bit in the rt confguration register equals 0 the illegalization table. bit equals 1 ** set message error (me) status. if not broadcast, transmit status word. if broadcast, also set status word bcr bit and suppress status response. dbac bit set. bcast bit updated. dpb bit toggles. ilcmd bit set. merr bit set. busid bit updated. rtrt bit reset. (other error bits reset.) ilcmd iwa ibr mode code command word is followed by a contiguous data word no status word transmit. set the message error (me) status bit. dbac bit set. bcast bit reset. dpb bit toggles. merr bit set. wcterr bit set. ilcmd bit reset. rtrt bit reset. (other error bits reset.) merr iwa * command is illegal but terminal is not using illegal command detection (in form response). ** command is illegal and terminal is using illegal command detection *** undefned mode command rendered invalid by umcinv option bit. command s bit in illegalization table is dont care. HI-6130, hi-6131
holt integrated circuits 255 circumstances for received message terminal response to received command bits updated in descriptor control word bits updated in data buffer msg info word interrupt options initiate self test (mc3): mode code command with mode code 00011 and t/ r bit equals 1 default response: reset message error (me) status then transmit status word. if broadcast, set the status word bcr bit and suppress status transmit. host should initiate self- test then update built-in test word at shared ram address 0x0093. resume terminal execution. dbac bit reset. bcast bit updated. dpb bit toggles. normal cs update: busid bit updated. merr bit reset. ilcmd bit reset. rtrt bit reset. (all error bits reset.) iwa ibr mc3 exceptions: invalid command word. or t/ r bit equals 0 and umcinv bit in the rt confguration register equals 1 *** no terminal response, the message is ignored. no status word change. (mode code is undefned when t/ r bit equals 0) no change no message info word is written none t/ r bit equals 0 and umcinv bit in the rt confguration register equals 0. the illegalization table bit equals 0 * respond in form: reset message error (me) status. if not broadcast, transmit status word. if broadcast, set the bcr status bit and suppress status response. dbac bit set. bcast bit updated. dpb bit toggles. normal cs update: busid bit updated. merr bit reset. ilcmd bit reset. rtrt bit reset. (other error bits reset.) iwa ibr t/ r bit equals 0 and umcinv bit in the rt confguration register equals 0. the illegalization table bit equals 1 ** set message error (me) status. if not broadcast, transmit status word. if broadcast, also set status word bcr bit and suppress status response. dbac bit set. bcast bit updated. dpb bit toggles. ilcmd bit set. merr bit set. busid bit updated. rtrt bit reset. (other error bits reset.) ilcmd iwa ibr mode code command word is followed by a contiguous data word no status word transmit. set the message error (me) status bit. dbac bit set. bcast bit reset. dpb bit toggles. merr bit set. wcterr bit set. busid bit updated. ilcmd bit reset. rtrt bit reset. (other error bits reset.) merr iwa * command is illegal but terminal is not using illegal command detection (in form response). ** command is illegal and terminal is using illegal command detection *** undefned mode command rendered invalid by umcinv option bit. command s bit in illegalization table is dont care. HI-6130, hi-6131
holt integrated circuits 256 circumstances for received message terminal response to received command bits updated in descriptor control word bits updated in data buffer msg info word interrupt options transmitter shutdown (mc4): mode code command with mode code 00100 and t/ r bit equals 1 default response: reset message error (me) status then transmit status word. if broadcast, set status word bcr bit and suppress status. transmit. after status trans- mission, inhibit the inactive bus: dbac bit reset. bcast bit updated. dpb bit toggles. normal cs update: busid bit updated. merr bit reset. ilcmd bit reset. rtrt bit reset. (all error bits reset.) iwa ibr the device automatically shuts down either transmit and receive or transmit only for the inactive bus, depending on the state of the bsdtxo bit in the master confguration register . refer to the description of the autobsd bit in the rt confguration register for further information. when mc4 results in transmitter shutdown, the condition is refected by assertion of a txasd or txbsd bit in the corresponding rt built-in test register at register address 0x001e (rt1) or address 0x0027 (rt2). if bsdtxo equals logic 0, an rxasd or rxbsd bit will also be asserted, indicating full bus shutdown (transmit and receive). once shutdown, the inactive bus transmitter (or transmitter and receiver) can be reactivated by an override transmitter shutdown mc5 or mc21 or reset remote terminal mc8 mode code command, or by software reset (initiated by setting the rt1reset or rt2reset bit in the master status and reset register 0x0001) or by hardware reset initiated by asserting the mr master reset input pin. mc4 exceptions: invalid command word. or t/ r bit equals 0 and umcinv bit in the rt confguration register equals 1 *** no terminal response, the message is ignored. no status word change. (mode code is undefned when t/ r bit equals 0) no change no message info word is written none t/ r bit equals 0 and umcinv bit in the rt confguration register equals 0. the illegalization table bit equals 0 * respond in form: reset message error (me) status. if not broadcast, transmit status word. if broadcast, set the bcr status bit and suppress status response. dbac bit set. bcast bit updated. dpb bit toggles. normal cs update: busid bit updated. merr bit reset. ilcmd bit reset. rtrt bit reset. (other error bits reset.) iwa ibr t/ r bit equals 0 and umcinv bit in the rt confguration register equals 0. the illegalization table bit equals 1 ** set message error (me) status. if not broadcast, transmit status word. if broadcast, also set status word bcr bit and suppress status response. dbac bit set. bcast bit updated. dpb bit toggles. ilcmd bit set. merr bit set. busid bit updated. rtrt bit reset. (other error bits reset.) ilcmd iwa ibr mode code command word is followed by a contiguous data word no status word transmit. set the message error (me) status bit. dbac bit set. bcast bit reset. dpb bit toggles. merr bit set. wcterr bit set. busid bit updated. ilcmd bit reset. rtrt bit reset. (other error bits reset.) merr iwa * command is illegal but terminal is not using illegal command detection (in form response). ** command is illegal and terminal is using illegal command detection *** undefned mode command rendered invalid by umcinv option bit. command s bit in illegalization table is dont care. HI-6130, hi-6131
holt integrated circuits 257 circumstances for received message terminal response to received command bits updated in descriptor control word bits updated in data buffer msg info word interrupt options override transmitter shutdown (mc5): mode code command with mode code 00101 and t/ r bit equals 1 default response: reset message error (me) status then transmit status word. if broadcast, set the status word bcr bit and suppress status transmit. this command is only used with dual redundant buses. after status transmission, reactivate inactive bus: dbac bit reset. bcast bit updated. dpb bit toggles. normal cs update: busid bit updated. merr bit reset. ilcmd bit reset. rtrt bit reset. (all error bits reset.) iwa ibr the device automatically re-enables transmit and receive for the inactive bus, without considering bsdtxo bit status in the master confguration register. the device affrms re-enabled bus status by resetting all four txasd, txbsd, rxasd and rxbsd shutdown status bits in the built-in test register at register address 0x001e for rt1 or 0x0027 for rt2. note: if the txinha or txinhb input pins are asserted, the device cannot override the resulting hardware transmit inhibit for the affected bus. in this case, the corresponding txasd and/or txbsd bits remain high. see built-in test register description for further information. mc5 exceptions: invalid command word. or t/ r bit equals 0 and umcinv bit in the rt confguration register equals 1 *** no terminal response, the message is ignored. no status word change. (mode code is undefned when t/ r bit equals 0) no change no message info word is written none t/ r bit equals 0 and umcinv bit in the rt confguration register equals 0. the illegalization table bit equals 0 * respond in form: reset message error (me) status. if not broadcast, transmit status word. if broadcast, set the bcr status bit and suppress status response. dbac bit set. bcast bit updated. dpb bit toggles. normal cs update: busid bit updated. merr bit reset. ilcmd bit reset. rtrt bit reset. (other error bits reset.) iwa ibr t/ r bit equals 0 and umcinv bit in the rt confguration register equals 0. the illegalization table bit equals 1 ** set message error (me) status. if not broadcast, transmit status word. if broadcast, also set status word bcr bit and suppress status response. dbac bit set. bcast bit updated. dpb bit toggles. ilcmd bit set. merr bit set. busid bit updated. rtrt bit reset. (other error bits reset.) ilcmd iwa ibr mode code command word is followed by a contiguous data word no status word transmit. set the message error (me) status bit. dbac bit set. bcast bit reset. dpb bit toggles. merr bit set. wcterr bit set. busid bit updated. ilcmd bit reset. rtrt bit reset. (other error bits reset.) merr iwa * command is illegal but terminal is not using illegal command detection (in form response). ** command is illegal and terminal is using illegal command detection *** undefned mode command rendered invalid by umcinv option bit. command s bit in illegalization table is dont care. HI-6130, hi-6131
holt integrated circuits 258 circumstances for received message terminal response to received command bits updated in descriptor control word bits updated in data buffer msg info word interrupt options inhibit terminal flag bit (mc6): mode code command with mode code 00110 and t/ r bit equals 1 default response: reset message error (me) status then transmit status word. if broadcast, set the status word bcr bit and suppress status transmit. dbac bit reset. bcast bit updated. dpb bit toggles. normal cs update: busid bit updated. merr bit reset. ilcmd bit reset. rtrt bit reset. (all error bits reset.) iwa ibr the device automatically sets the tf inhibit bit in the bit word register at address 0x0013. while the tf inhibit bit is set, the device disregards assertion of the terminal flag (tf) bit in the 1553 status bits register (0x0006) and only transmits status with the terminal flag status bit reset. once the terminal flag has been inhibited, it can be reactivated by an override inhibit terminal flag mc7 or reset remote terminal mc8 mode command, by software reset (asserting the srst bit in the rt confguration register) or by asserting the mr master reset input pin. mc6 exceptions: invalid command word. or t/ r bit equals 0 and umcinv bit in the rt confguration register equals 1 *** no terminal response, the message is ignored. no status word change. (mode code is undefned when t/ r bit equals 0) no change no message info word is written none t/ r bit equals 0 and umcinv bit in the rt confguration register equals 0. the illegalization table bit equals 0 * respond in form: reset message error (me) status. if not broadcast, transmit status word. if broadcast, set the bcr status bit and suppress status response. dbac bit set. bcast bit updated. dpb bit toggles. normal cs update: busid bit updated. merr bit reset. ilcmd bit reset. rtrt bit reset. (other error bits reset.) iwa ibr t/ r bit equals 0 and umcinv bit in the rt confguration register equals 0. the illegalization table bit equals 1 ** set message error (me) status. if not broadcast, transmit status word. if broadcast, also set status word bcr bit and suppress status response. dbac bit set. bcast bit updated. dpb bit toggles. ilcmd bit set. merr bit set. busid bit updated. rtrt bit reset. (other error bits reset.) ilcmd iwa ibr mode code command word is followed by a contiguous data word no status word transmit. set the message error (me) status bit. dbac bit set. bcast bit reset. dpb bit toggles. merr bit set. wcterr bit set. busid bit updated. ilcmd bit reset. rtrt bit reset. (other error bits reset.) merr iwa * command is illegal but terminal is not using illegal command detection (in form response). ** command is illegal and terminal is using illegal command detection *** undefned mode command rendered invalid by umcinv option bit. command s bit in illegalization table is dont care. HI-6130, hi-6131
holt integrated circuits 259 circumstances for received message terminal response to received command bits updated in descriptor control word bits updated in data buffer msg info word interrupt options override inhibit terminal flag bit (mc7): mode code command with mode code 00111 and t/ r bit equals 1 default response: reset message error (me) status then transmit status word. if broadcast, set the status word bcr bit and suppress status transmit. dbac bit reset. bcast bit updated. dpb bit toggles. normal cs update: busid bit updated. merr bit reset. ilcmd bit reset. rtrt bit reset. (all error bits reset.) iwa ibr the device automatically resets the tf inhibit bit in the bit word register at address 0x0013. while the tf inhibit bit is reset, the device transmits status with the terminal flag status bit set if the terminal flag (tf) bit is asserted in the 1553 status bits register (0x0006). mc7 exceptions: invalid command word. or t/ r bit equals 0 and umcinv bit in the rt confguration register equals 1 *** no terminal response, the message is ignored. no status word change. (mode code is undefned when t/ r bit equals 0) no change no message info word is written none t/ r bit equals 0 and umcinv bit in the rt confguration register equals 0. the illegalization table bit equals 0 * respond in form: reset message error (me) status. if not broadcast, transmit status word. if broadcast, set the bcr status bit and suppress status response. dbac bit set. bcast bit updated. dpb bit toggles. normal cs update: busid bit updated. merr bit reset. ilcmd bit reset. rtrt bit reset. (other error bits reset.) iwa ibr t/ r bit equals 0 and umcinv bit in the rt confguration register equals 0. the illegalization table bit equals 1 ** set message error (me) status. if not broadcast, transmit status word. if broadcast, also set status word bcr bit and suppress status response. dbac bit set. bcast bit updated. dpb bit toggles. ilcmd bit set. merr bit set. busid bit updated. rtrt bit reset. (other error bits reset.) ilcmd iwa ibr mode code command word is followed by a contiguous data word no status word transmit. set the message error (me) status bit. dbac bit set. bcast bit reset. dpb bit toggles. merr bit set. wcterr bit set. busid bit updated. ilcmd bit reset. rtrt bit reset. (other error bits reset.) merr iwa * command is illegal but terminal is not using illegal command detection (in form response). ** command is illegal and terminal is using illegal command detection *** undefned mode command rendered invalid by umcinv option bit. command s bit in illegalization table is dont care. HI-6130, hi-6131
holt integrated circuits 260 circumstances for received message terminal response to received command bits updated in descriptor control word bits updated in data buffer msg info word interrupt options reset remote terminal (mc8): mode code command with mode code 01000 and t/ r bit equals 1 default response: reset message error (me) status. if not broadcast, transmit status word. dbac bit reset. bcast bit updated. dpb bit toggles. normal cs update: busid bit updated. merr bit reset. ilcmd bit reset. rtrt bit reset. (all error bits reset.) iwa ibr after status transmission, the device automatically resets the status message error (me) busy and broadcast command received (bcr) bits in its internal status register. the bit word at shared ram address is reset to 0x0000. if either transmitter was shutdown, the shutdown condition is overridden. if the terminal flag (tf) status bit was inhibited, the inhibit is reset. this command does not reset any of the host-programmed registers that confgure the terminal for operation. to complete the terminal reset process, the host must assert either mr hardware master reset (with or without auto-initialization) or assert the srst bit in the rt confguration register to execute software reset. see following section entitled reset and initialization for additional details. because mc8 requires host interaction, most applications will probably utilize the iwa interrupt to alert the host when received. mc8 exceptions: invalid command word. or t/ r bit equals 0 and umcinv bit in the rt confguration register equals 1 *** no terminal response, the message is ignored. no status word change. (mode code is undefned when t/ r bit equals 0) no change no message info word is written none t/ r bit equals 0 and umcinv bit in the rt confguration register equals 0. the illegalization table bit equals 0 * respond in form: reset message error (me) status. if not broadcast, transmit status word. if broadcast, set the bcr status bit and suppress status response. dbac bit set. bcast bit updated. dpb bit toggles. normal cs update: busid bit updated. merr bit reset. ilcmd bit reset. rtrt bit reset. (other error bits reset.) iwa ibr t/ r bit equals 0 and umcinv bit in the rt confguration register equals 0. the illegalization table bit equals 1 ** set message error (me) status. if not broadcast, transmit status word. if broadcast, also set status word bcr bit and suppress status response. dbac bit set. bcast bit updated. dpb bit toggles. ilcmd bit set. merr bit set. busid bit updated. rtrt bit reset. (other error bits reset.) ilcmd iwa ibr mode code command word is followed by a contiguous data word no status word transmit. set the message error (me) status bit. dbac bit set. bcast bit reset. dpb bit toggles. merr bit set. gaperr bit set. busid bit updated. ilcmd bit reset. rtrt bit reset. (other error bits reset.) merr iwa * command is illegal but terminal is not using illegal command detection (in form response). ** command is illegal and terminal is using illegal command detection *** undefned mode command rendered invalid by umcinv option bit. command s bit in illegalization table is dont care. HI-6130, hi-6131
holt integrated circuits 261 circumstances for received message terminal response to received command bits updated in descriptor control word bits updated in data buffer msg info word interrupt options reserved mode codes mc9 - mc15: mode code command with mode codes 01001 through 01111 and t/ r bit equals 1 the reserved mode code commands do not have defned terminal actions. host must initialize device to respond using either of the two following methods: the mode codes bit in illegalization table equals 0 * or the mode codes bit in illegalization table equals 1 ** rt is not using illegal command detection. respond in form: reset message error (me) status and transmit status word. or rt is using illegal command detectionand mode code is illegalized. set message error (me) status and transmit status word. dbac bit set. bcast bit updated. dpb bit toggles. dbac bit set. bcast bit updated. dpb bit toggles. normal cs update: busid bit reset. merr bit reset. ilcmd bit reset. rtrt bit reset. (all error bits reset.) ilcmd bit set. busid bit updated. merr bit set. rtrt bit reset. (other error bits reset.) iwa ilcmd iwa mc9 - mc15 exceptions: invalid command word. or t/ r bit equals 0 and umcinv bit in the rt confg. reg. equals 1 *** no terminal response, the message is ignored. no status word change. (mode code is undefned when t/ r bit equals 0) no change no message info word is written none t/ r bit equals 0 and umcinv bit in the rt confg. reg. equals 0. the illegalization table bit equals 0 * respond in form: reset message error (me) status. if not broadcast, transmit status word. if broadcast, set the bcr status bit and suppress status response. dbac bit set. bcast bit updated. dpb bit toggles. normal cs update: busid bit updated. merr bit reset. ilcmd bit reset. rtrt bit reset. (other error bits reset.) iwa ibr t/ r bit equals 0 and umcinv bit in the rt confg. reg. equals 0. the illegalization table bit equals 1 ** set message error (me) status. if not broadcast, transmit status word. if broadcast, also set status word bcr bit and suppress status response. dbac bit set. bcast bit updated. dpb bit toggles. ilcmd bit set. merr bit set. busid bit updated. rtrt bit reset. (other error bits reset.) ilcmd iwa ibr mode code command word is followed by a contiguous data word no status word transmit. set the message error (me) status bit. dbac bit set. bcast bit reset. dpb bit toggles. merr bit set. wcterr bit set. busid bit updated. ilcmd bit reset. rtrt bit reset. (other error bits reset.) merr iwa * command is illegal but terminal is not using illegal command detection (in form response). ** command is illegal and terminal is using illegal command detection *** undefned mode command rendered invalid by umcinv option bit. command s bit in illegalization table is dont care. HI-6130, hi-6131
holt integrated circuits 262 circumstances for received message terminal response to received command bits updated in descriptor control word bits updated in data buffer msg info word interrupt options transmit vector word (mc16): mode code command with mode code 10000 and t/ r bit equals 1 default cs response: reset message error (me) and bcr status bits. then transmit status word followed by the data word stored in the assigned index or ping-pong data buffer (or in descriptor word 4 for smcp simplifed mode command processing). dbac bit reset. bcast bit reset. dpb bit toggles. normal cs update: busid bit updated. merr bit reset. ilcmd bit reset. rtrt bit reset. (all error bits reset.) iwa mc16 exceptions: broadcast address rt31 (broadcast not allowed) no status word transmit. set the message error (me) and bcr status bits. dbac bit set. bcast bit set. dpb toggles. merr bit set. busid bit updated. ilcmd bit reset. rtrt bit reset. (other error bits reset.) merr iwa ibr invalid command word. or t/ r bit equals 0 and umcinv bit in the rt confguration register equals 1 *** no terminal response, the message is ignored. no status word change. (mode code is undefned when t/ r bit equals 0) no change no message info word is written none t/ r bit equals 0 and umcinv bit in the rt confguration register equals 0. the illegalization table bit equals 0 * respond in form: reset message error (me) status. if not broadcast, transmit status word. if broadcast, set the bcr status bit and suppress status response. dbac bit set. bcast bit updated. dpb bit toggles. normal cs update: busid bit updated. merr bit reset. ilcmd bit reset. rtrt bit reset. (other error bits reset.) iwa ibr t/ r bit equals 0 and umcinv bit in the rt confguration register equals 0. the illegalization table bit equals 1 ** set message error (me) status. if not broadcast, transmit status word. if broadcast, also set status word bcr bit and suppress status response. dbac bit set. bcast bit updated. dpb bit toggles. ilcmd bit set. merr bit set. busid bit updated. rtrt bit reset. (other error bits reset.) ilcmd iwa ibr mode code command word is followed by a contiguous data word no status word transmit. set the message error (me) status bit. if broadcast, set the bcr status bit. dbac bit set. bcast bit reset. dpb bit toggles. merr bit set. wcterr bit set. busid bit updated. ilcmd bit reset. rtrt bit reset. (other error bits reset.) merr iwa ibr * command is illegal but terminal is not using illegal command detection (in form response). ** command is illegal and terminal is using illegal command detection *** undefned mode command rendered invalid by umcinv option bit. command s bit in illegalization table is dont care. HI-6130, hi-6131
holt integrated circuits 263 circumstances for received message terminal response to received command bits updated in descriptor control word bits updated in data buffer msg info word interrupt options synchronize with data word (mc17): mode code command with mode code 10001 and t/ r bit equals 1 default response: reset message error (me) status. and transmit status word. if broadcast, set bcr status bit and suppress status response. dbac bit reset. bcast bit reset. dpb bit toggles. normal cs update: busid bit updated. merr bit reset. ilcmd bit reset. rtrt bit reset. (all error bits reset.) iwa device stores received data word in the assigned ping-pong or index data buffer (or in descriptor word 4 for smcp simplifed mode command processing). rt confguration register mcopt2 and mcopt3 bits allow automatic time-tag count loading using the data word received. if mcopt2 equals 1, the received data word is automatically loaded to the time-tag counter if the low order bit of the received data word (bit 0 equals 0. if mcopt3 equals 1, the received data word is automatically loaded to the time-tag counter if the low order bit of the received data word (bit 0) equals 1. if both bits are set, the received data word is unconditionally loaded into the time-tag counter. for non-broadcast commands, counter load occurs before status word transmission. mc17 exceptions: invalid command word. or t/ r bit equals 0 and umcinv bit in the rt confg. reg. equals 1 *** no terminal response, the message is ignored. no status word change. (mode code is undefned when t/ r bit equals 0) no change no message info word is written none t/ r bit equals 0 and umcinv bit in the rt confg. reg. equals 0. the illegalization table bit equals 0 * respond in form: reset message error (me) status. if not broadcast, transmit status word. if broadcast, set the bcr status bit and suppress status response. dbac bit set. bcast bit updated. dpb bit toggles. normal cs update: busid bit updated. merr bit reset. ilcmd bit reset. rtrt bit reset. (other error bits reset.) iwa ibr t/ r bit equals 0 and umcinv bit in the rt confg. reg. equals 0. the illegalization table bit equals 1 ** no status word transmit. set the message error (me) status bit. if broadcast, set the bcr status bit. dbac bit set. bcast bit updated. dpb bit toggles. ilcmd bit set. merr bit set. busid bit updated. rtrt bit reset. (other error bits reset.) ilcmd iwa ibr mode code command word not followed by a contiguous data word (missing data word) no status word transmit. set the message error (me) status bit. if broadcast, set the bcr status bit. dbac bit set. bcast bit reset. dpb bit toggles. merr bit set. wcterr bit set. busid bit updated. ilcmd bit reset. rtrt bit reset. (other error bits reset.) merr iwa ibr mode code command word followed by data word with manchester encoding or parity error (bad data word) no status word transmit. set the message error (me) status bit. if broadcast, set the bcr status bit. dbac bit set. bcast bit updated. dpb bit toggles. merr bit set. iwderr bit set. busid bit updated. ilcmd bit reset. rtrt bit reset. (other error bits reset.) merr iwa ibr * command is illegal but terminal is not using illegal command detection (in form response). ** command is illegal and terminal is using illegal command detection *** undefned mode command rendered invalid by umcinv option bit. command s bit in illegalization table is dont care. HI-6130, hi-6131
holt integrated circuits 264 circumstances for received message terminal response to received command bits updated in descriptor control word bits updated in data buffer msg info word interrupt options transmit last command (mc18): mode code command with mode code 10010 and t/ r bit equals 1 default response: status is not updated. transmit status word from the previous command, with data word containing the last valid command word (assuming it was not a transmit status or a transmit last command mode command. dbac bit reset. bcast bit reset. dpb bit toggles. normal cs update: busid bit updated. merr bit reset. ilcmd bit reset. rtrt bit reset. (all error bits reset.) iwa transmitted data word is automatically provided from an internal register, and is copied to assigned index or ping- pong buffer (or to descriptor word 4 for smcp simplifed mode command processing) mc18 exceptions: broadcast address rt31 (broadcast not allowed) no status word transmit. set the message error (me) and bcr status bits. dbac bit set. bcast bit set. dpb toggles. merr bit set. busid bit updated. ilcmd bit reset. rtrt bit reset. (other error bits reset.) merr iwa ibr invalid command word. or t/ r bit equals 0 and umcinv bit in the rt confguration register equals 1 *** no terminal response, the message is ignored. no status word change. (mode code is undefned when t/ r bit equals 0) no change no message info word is written none t/ r bit equals 0 and umcinv bit in the rt confguration register equals 0. the illegalization table bit equals 0 * respond in form: reset message error (me) status. if not broadcast, transmit status word. if broadcast, set the bcr status bit and suppress status response. dbac bit set. bcast bit updated. dpb bit toggles. normal cs update: busid bit updated. merr bit reset. ilcmd bit reset. rtrt bit reset. (other error bits reset.) iwa ibr t/ r bit equals 0 and umcinv bit in the rt confguration register equals 0. the illegalization table bit equals 1 ** set message error (me) status. if not broadcast, transmit status word. if broadcast, also set status word bcr bit and suppress status response. dbac bit set. bcast bit updated. dpb bit toggles. ilcmd bit set. merr bit set. busid bit updated. rtrt bit reset. (other error bits reset.) ilcmd iwa ibr mode code command word is followed by a contiguous data word no status word transmit. set the message error (me) status bit. if broadcast, set the bcr status bit. dbac bit set. bcast bit reset. dpb bit toggles. merr bit set. wcterr bit set. busid bit updated. ilcmd bit reset. rtrt bit reset. (other error bits reset.) merr iwa ibr * command is illegal but terminal is not using illegal command detection (in form response). ** command is illegal and terminal is using illegal command detection *** undefned mode command rendered invalid by umcinv option bit. command s bit in illegalization table is dont care. HI-6130, hi-6131
holt integrated circuits 265 circumstances for received message terminal response to received command bits updated in descriptor control word bits updated in data buffer msg info word interrupt options transmit bit word (mc19): mode code command with mode code 10011 and t/ r bit equals 1 default response: reset message error (me) and bcr status bits. then transmit status word followed by data word from either bit word register or alternate bit word register, depending on confguration reg. 2 option bit altbitw. dbac bit reset. bcast bit reset. dpb bit toggles. normal cs update: busid bit reset. merr bit reset. ilcmd bit reset. rtrt bit reset. (all error bits reset.) iwa transmitted data word is automatically copied to the assigned index or ping-pong buffer (or to descriptor word 4 for smcp simplifed mode command processing) mc19 exceptions: broadcast address rt31 (broadcast not allowed) no status word transmit. set the message error (me) and bcr status bits. dbac bit set. bcast bit set. dpb toggles. merr bit set. busid bit updated. ilcmd bit reset. rtrt bit reset. (other error bits reset.) merr iwa ibr invalid command word. or t/ r bit equals 0 and umcinv bit in the rt confguration register equals 1 *** no terminal response, the message is ignored. no status word change. (mode code is undefned when t/ r bit equals 0) no change no message info word is written none t/ r bit equals 0 and umcinv bit in the rt confguration register equals 0. the illegalization table bit equals 0 * respond in form: reset message error (me) status. if not broadcast, transmit status word. if broadcast, set the bcr status bit and suppress status response. dbac bit set. bcast bit updated. dpb bit toggles. normal cs update: busid bit updated. merr bit reset. ilcmd bit reset. rtrt bit reset. (other error bits reset.) iwa ibr t/ r bit equals 0 and umcinv bit in the rt confguration register equals 0. the illegalization table bit equals 1 ** set message error (me) status. if not broadcast, transmit status word. if broadcast, also set status word bcr bit and suppress status response. dbac bit set. bcast bit updated. dpb bit toggles. ilcmd bit set. merr bit set. busid bit updated. rtrt bit reset. (other error bits reset.) ilcmd iwa ibr mode code command word is followed by a contiguous data word no status word transmit. set the message error (me) status bit. if broadcast, set the bcr status bit. dbac bit set. bcast bit reset. dpb bit toggles. merr bit set. wcterr bit set. busid bit updated. ilcmd bit reset. rtrt bit reset. (other error bits reset.) merr iwa ibr * command is illegal but terminal is not using illegal command detection (in form response). ** command is illegal and terminal is using illegal command detection *** undefned mode command rendered invalid by umcinv option bit. command s bit in illegalization table is dont care. HI-6130, hi-6131
holt integrated circuits 266 circumstances for received message terminal response to received command bits updated in descriptor control word bits updated in data buffer msg info word interrupt options selected transmitter shutdown (mc20): mode code command with mode code 10100 and t/ r bit equals 1 default response: reset message error (me) status. and transmit status word. if broadcast, set bcr status bit and suppress status response. this command is intended for use in 1553 systems with more than one dual redundant bus. dbac bit reset. bcast bit reset. dpb bit toggles. normal cs update: busid bit updated. merr bit reset. ilcmd bit reset. rtrt bit reset. (all error bits reset.) iwa after status word transmission, the device stores received data word in the assigned index or ping-pong buffer (or in descriptor word 4 if smcp simplifed mode command processing applies). if the autobsd bit in the rt confguration register equals 1, the received data word is compared to the value in the bus select register corresponding to the inactive bus. for example, if the command is received on bus a, the comparison uses the bus b select register value. if the compared values match, the device automatically shuts down either transmit and receive or transmit only for the inactive bus, depending on the state of the bsdtxo bit in the master confguration register 0x0000. see descriptions for the bsdtxo bit in master confguration register and the autobsd bit in the rt confguration register(s) for further information. when a bus transmitter (or transmitter and receiver) is shut down by this mode command, bus status is refected by assertion of a txasd or txbsd bit in the rt built-in test register at register address 0x001e for rt1, 0x0027 for rt2. if bsdtxo equals logic 0, an rxasd or rxbsd bit will also be asserted. see rt built-in test register description for further information. if the autobsd bit in the rt confguration register equals 0, the iwa interrupt is typically used to alert the host when an mc20 command is received. the host must evaluate whether the received mode data word matches the bus selection criteria. if bus selection match occurs, the host fulflls bus shutdown command using one of two options: 1. set the bus shutdown bit inhbusa or inhbusb for the inactive bus in the rt confguration register(s) to inhibit both transmit and receive, or 2. assert the transmit shutdown input pin txinha or txinhb for the inactive bus to inhibit only transmit . the inactive bus receiver remains active; all valid commands are heeded without transmit. this option is rarely applied. once shutdown, the inactive bus transmitter (or transmitter and receiver) can be reactivated fve ways: an override transmitter shutdown mc5, a mc21 command with data word that matches bus select criteria, a reset remote terminal mc8 mode code command, a software reset initiated by setting the rt1reset or rt2reset bit in the master status and reset register 0x0001, or by hardware reset initiated by asserting the mr master reset input pin. mc20 exceptions: invalid command word. or t/ r bit equals 0 and umcinv bit in the rt confguration register equals 1 *** no terminal response, the message is ignored. no status word change. (mode code is undefned when t/ r bit equals 0) no change no message info word is written none HI-6130, hi-6131
holt integrated circuits 267 circumstances for received message terminal response to received command bits updated in descriptor control word bits updated in data buffer msg info word interrupt options t/ r bit equals 0 and umcinv bit in the rt confguration register equals 0. the illegalization table bit equals 0 * respond in form: reset message error (me) status. if not broadcast, transmit status word. if broadcast, set the bcr status bit and suppress status response. dbac bit set. bcast bit updated. dpb bit toggles. normal cs update: busid bit updated. merr bit reset. ilcmd bit reset. rtrt bit reset. (other error bits reset.) iwa ibr t/ r bit equals 0 and umcinv bit in the rt confguration register equals 0. the illegalization table bit equals 1 ** set message error (me) status. if not broadcast, transmit status word. if broadcast, also set status word bcr bit and suppress status response. dbac bit set. bcast bit updated. dpb bit toggles. ilcmd bit set. merr bit set. busid bit updated. rtrt bit reset. (other error bits reset.) ilcmd iwa ibr mode code command word not followed by a contiguous data word (missing data word) no status word transmit. set the message error (me) status bit. if broadcast, set the bcr status bit. dbac bit set. bcast bit updated. dpb bit toggles. merr bit set. wcterr bit updated. busid bit updated. ilcmd bit reset. rtrt bit reset. (other error bits reset.) merr iwa ibr mode code command word followed by data word with manchester encoding or parity error (bad data word) no status word transmit. set the message error (me) status bit. if broadcast, set the bcr status bit. dbac bit set. bcast bit updated. dpb bit toggles. merr bit set. iwderr bit set. busid bit updated. ilcmd bit reset. rtrt bit reset. (other error bits reset.) merr iwa ibr * command is illegal but terminal is not using illegal command detection (in form response). ** command is illegal and terminal is using illegal command detection *** undefned mode command rendered invalid by umcinv option bit. command s bit in illegalization table is dont care. HI-6130, hi-6131
holt integrated circuits 268 circumstances for received message terminal response to received command bits updated in descriptor control word bits updated in data buffer msg info word interrupt options override selected transmitter shutdown (mc21): mode code command with mode code 10101 and t/ r bit equals 1 default response: reset message error (me) status. and transmit status word. if broadcast, set the bcr status bit and suppress status response. dbac bit reset. bcast bit reset. dpb bit toggles. normal cs update: busid bit updated. merr bit reset. ilcmd bit reset. rtrt bit reset. (all error bits reset.) iwa after status word transmission, the device stores the received data word in the assigned index or ping-pong buffer (or in descriptor word 4 if smcp simplifed mode command processing applies). if the autobsd bit in the rt confguration register equals 1, the received data word is compared to the value in the bus select register corresponding to the inactive bus. for example, if the command is received on bus a, the comparison uses the bus b select register value. if the compared values match, the device automatically re-enables transmit and receive for the inactive bus, regardless of the state of the bsdtxo bit in the master confguration register. the device affrms fully re-enabled bus status by resetting all four txasd, txbsd, rxasd and/or rxbsd bits in the rt built-in test register at register address 0x001e for rt1, address 0x0027 for rt2. note: if the txinha or txinhb input pins are asserted, the device cannot override the resulting hardware transmit inhibit for the affected bus. in this case, the corresponding txasd and/or txbsd bits remain high. see rt built-in test register description for further information. if the autobsd bit in the master confguration register equals 0, the iwa interrupt is typically used to alert the host when an mc21 command is received. the host must evaluate whether the received mode data word matches the bus selection criteria. if bus selection match occurs, the host fulflls the override shutdown command using one of two options: 1. reset the rtinha or rtinhb bus shutdown bit corresponding to the inactive bus in the applicable rt confgu - ration register to re-enable both transmit and receive, if the host used this bit to shut down transmit and receive for an earlier mc4 or mc20 command. note: resetting the rtinha or rtinhb shutdown bit cannot restore bus transmit capability if the txinha or txinhb input pin is asserted, or 2. reset the transmit shutdown input pin txinha or txinhb for the inactive bus to re-enable transmit if the host used this pin to shut down transmit only for an earlier mc4 or mc20 command. mc21 exceptions: invalid command word. or t/ r bit equals 0 and umcinv bit in the rt confguration register equals 1 *** no terminal response, the message is ignored. no status word change. (mode code is undefned when t/ r bit equals 0) no change no message info word is written none HI-6130, hi-6131
holt integrated circuits 269 circumstances for received message terminal response to received command bits updated in descriptor control word bits updated in data buffer msg info word interrupt options t/ r bit equals 0 and umcinv bit in the rt confguration register equals 0. the illegalization table bit equals 0 * respond in form: reset message error (me) status. if not broadcast, transmit status word. if broadcast, set the bcr status bit and suppress status response. dbac bit set. bcast bit updated. dpb bit toggles. normal cs update: busid bit updated. merr bit reset. ilcmd bit reset. rtrt bit reset. (other error bits reset.) iwa ibr t/ r bit equals 0 and umcinv bit in the rt confguration register equals 0. the illegalization table bit equals 1 ** set message error (me) status. if not broadcast, transmit status word. if broadcast, also set status word bcr bit and suppress status response. dbac bit set. bcast bit updated. dpb bit toggles. ilcmd bit set. merr bit set. busid bit updated. rtrt bit reset. (other error bits reset.) ilcmd iwa ibr mode code command word not followed by a contiguous data word (missing data word) no status word transmit. set the message error (me) status bit. if broadcast, set the bcr status bit. dbac bit set. bcast bit updated. dpb bit toggles. merr bit set. wcterr bit set. busid bit updated. ilcmd bit reset. rtrt bit reset. (other error bits reset.) merr iwa ibr mode code command word followed by data word with manchester encoding or parity error (bad data word) no status word transmit. set the message error (me) status bit. if broadcast, set the bcr status bit. dbac bit set. bcast bit updated. dpb bit toggles. merr bit set. iwderr bit set. busid bit updated. ilcmd bit reset. rtrt bit reset. (other error bits reset.) merr iwa ibr * command is illegal but terminal is not using illegal command detection (in form response). ** command is illegal and terminal is using illegal command detection *** undefned mode command rendered invalid by umcinv option bit. command s bit in illegalization table is dont care. HI-6130, hi-6131
holt integrated circuits 270 circumstances for received message terminal response to received command bits updated in descriptor control word bits updated in data buffer msg info word interrupt options reserved mode codes mc22 - mc31: mode code commands having mode codes 10110 through 11111 the reserved mode code commands do not have defned actions. host must initialize device to respond using either of the two following methods: the mode codes bit in illegalization table equals 1 ** (rt is using illegal command detection) or the mode codes bit in illegalization table equals 0 * (rt not using illegal command detection, respond in form) mode code is illegalized. set message error (me) status and transmit status word. if t/ r bit equals 1, suppress data word transmission. or if t/ r bit equals 1, reset message error (me) status. transmit status word with contiguous data word read from assigned index or ping- pong buffer (or from descriptor word 4 if the smcp option applies.) if t/ r bit equals 0, reset message error (me) status and transmit status. if broadcast, also set bcr status and suppress status transmit. device stores received data word in assigned index or ping- pong buffer (or in descriptor word 4 if smcp simplifed mode command processing applies). dbac bit set. bcast bit reset. dpb bit toggles. dbac bit set. bcast bit reset. dpb bit toggles. dbac bit reset. bcast bit updated. dpb bit toggles. ilcmd bit set. merr bit set. busid bit updated. rtrt bit reset. (other error bits reset.) normal cs update: busid bit updated. merr bit reset. ilcmd bit reset. rtrt bit reset. (all error bits reset.) normal cs update: busid bit updated. merr bit reset. ilcmd bit reset. rtrt bit reset (all error bits reset.) ilcmd iwa iwa iwa ibr mc22 - mc31 exceptions: invalid command word. no terminal response, the message is ignored. no status word change. no change no message info word is written none t/ r bit equals 0 and mode code command word is not followed by a contiguous data word (missing data word) no status word transmit. set the message error (me) status bit. if broadcast, set the bcr status bit. dbac bit set. bcast bit updated. dpb bit toggles. merr bit set. wcterr bit set. busid bit updated. ilcmd, rtrt bits reset. (other error bits reset.) merr iwa ibr HI-6130, hi-6131
holt integrated circuits 271 circumstances for received message terminal response to received command bits updated in descriptor control word bits updated in data buffer msg info word interrupt options t/ r bit equals 0 and command word is followed by data word with manchester or parity error (bad data word) no status word transmit. set the message error (me) status bit. if broadcast, set the bcr status bit. dbac bit set. bcast bit updated. dpb bit toggles. merr bit set. iwderr bit set. busid bit updated. ilcmd, rtrt bits reset. (other error bits reset.) merr iwa ibr t/ r bit equals 1 and mode code command word is followed by a contiguous data word no status word transmit. set the message error (me) status bit. dbac bit set. bcast bit reset. dpb bit toggles. merr, wcterr bits set. busid bit updated. ilcmd, rtrt bits reset. (other error bits reset.) merr iwa t/ r bit equals 1 and mode code command is addressed to rt31 no status word transmit. set the message error (me) and bcr status bits. dbac bit set. bcast bit set. dpb bit toggles. merr bit set. busid bit updated. ilcmd, rtrt bits reset. (other error bits reset.) merr iwa ibr * command is illegal but terminal is not using illegal command detection (in form response). ** command is illegal and terminal is using illegal command detection HI-6130, hi-6131
holt integrated circuits 272 27. electrical characteristics 27.1. absolute maximum ratings supply voltage (v dd ) -0.3 v to +5.0 v logic input voltage range -0.3 v to +3.6 v receiver differential voltage 10 vp-p driver peak output current +1.0 a power dissipation at 25c 1.0 w solder temperature 275 o c for 10 sec. junction temperature 175 o c storage temperature -65 o c to +150 o c 27.2. recommended operating conditions operating supply voltage (v dd ) 3.3 vdc 5% operating temperature range industrial extended -40 o c to +85 o c -55 o c to +125 o c note: stresses above absolute maximum ratings or outside recommended operating conditions may cause permanent damage to the device. these are stress ratings only. operation at the limits is not recommended. 27.3. dc electrical characteristics v dd = 3.3v, gnd = 0v, t a = operating temperature range (unless otherwise stated) parameters symbol test conditions limits unit min typ max operating voltage v dd 3.15 3.3 3.45 v power supply current see note 1 on next page i cc1 not transmitting - 4 10 ma i cc2 continuous supply current while one bus transmits @ 100% duty cycle, 70 resistive load - 720 760 ma power dissipation see note 2 on next page pd 1 not transmitting - - 60 mw pd 2 transmit one bus @ 100% duty cycle, 70 resistive load - 420 550 mw min. input voltage (high) v ih digital inputs 70% - - v dd max. input voltage (low) v il digital inputs - - 30% v dd max. input current (high): 39 inputs with pull-down. i ih digital inputs (each digital input pulled high) - - 100 a HI-6130, hi-6131
holt integrated circuits 273 parameters symbol test conditions limits unit min typ max max. input current (high): 39 inputs with pull-up. i ih digital inputs (each digital input pulled high) +1 - - a max. input current (low) 39 inputs with pull-up. i il digital inputs (each digital input pulled low) - - -100 a max. input current (low) 39 inputs with pull-down. i il digital inputs (each digital input pulled low) -1 - - a min. output voltage (high) v oh i out = -1.0ma, digital outputs 90% - - v dd max. output voltage (low) v ih i out = 1.0ma, digital outputs - - 10% v dd receiver (measured at point ad in figure 34 unless otherwise specifed) input resistance r in differential 20 - - k input capacitance c in differential - - 5 pf common mode rejection ratio cmrr 40 - - db input level v in differential - - 9 vp-p input common mode voltage v icm -5 - +5 v-pk threshold voltage (direct-coupled) detect v thd 1 mhz sine wave (measured at point ad in figure 34 ) 1.15 - 20.0 vp-p no detect v thnd - - 0.28 vp-p threshold voltage (transformer-coupled) detect v thd 1 mhz sine wave (measured at point at in figure 35 ) 0.86 - 14.0 vp-p no detect v thnd - - 0.2 vp-p transmitter (measured at point ad in figure 34 unless otherwise specifed) output voltage direct coupled v out 35 load 6.0 - 9.0 vp-p transformer coupled v out 70 load (measured at point at in figure 35 ) 18.0 - 27.0 vp-p output noise v on differential, inhibited - - 10.0 mvp-p output dynamic offset voltage direct coupled v dyn 35 load -90 - 90 mv transformer coupled v dyn 70 load (measured at point at in figure 35 ) -250 - 250 mv output resistance r out differential, not transmitting 10 - - k output capacitance c out 1 mhz sine wave - - 15 pf note 1: in actual use, the highest practical transmit duty cycle is 96%, occurring when a remote terminal responds to a series of 32 data word transmit commands (rt to bc) repeating with minimum intermessage gap of 4s (2s dead time) and typical hi- 6110 rt response delay of 5s. note 2: while one bus continuously transmits, the power delivered by the 3.3v power supply is 3.3v 720ma typical = 2.4w. of this, 420mw is dissipated in the device, the remainder in the load. HI-6130, hi-6131
holt integrated circuits 274 27.4. ac electrical characteristics D hi-6131 host bus interface timing v dd = 3.3v, gnd = 0v, t a = operating temperature range (unless otherwise stated) parameters symbol limits units min typ max hi-6131 interface timing (spi host bus interface) sck clock period t cyc 50 - - ns ce set-up time to frst sck rising edge t ces 25 - - ns ce hold time after last sck falling edge t ceh 25 - - ns ce inactive between spi instructions t cph 100 - - ns spi si data set-up time to sck rising edge t ds 10 - - ns spi si data hold time after sck rising edge t dh 10 - - ns sck high time t sckh 25 - - ns sck low time t sckl 100 - - ns so valid after sck falling edge t dv - - 20 ns so high-impedance after ce inactive t chz - - 75 ns ce sclk so chz t hi impedance sckh t t dv lsb cph t t sckl msb hi impedance serial output timing diagram serial input timing diagram ce sclk si msb ces t ds t t dh lsb cph t ceh t figure 29. hi-6131 host bus interface timing diagram HI-6130, hi-6131
holt integrated circuits 275 27.5. ac electrical characteristics D HI-6130 host bus interface timing parameters symbol limits units min typ max write timing write strobe t wr 55 - - ns write inactive time t inact 25 - - ns write cycle, t wr + t inact - 80 - - ns read timing wait assertion time t was 20 - - ns wait time t w - - 130 ns read strobe, sequential address, 8-bit bus mode t sr8 55 - - ns read strobe, sequential address, 16-bit bus mode t sr16 65 - - ns read strobe, non-sequential address t nsr 110 - - ns read inactive time t inact 25 - - ns read cycles in 8-bit bus mode (see note below) read cycle, sequential address, 8-bit bus mode, t sr8 + t inact - 80 - - ns read cycle, non-sequential address, 8-bit bus mode, t was + t w + t sr8 + t inact - - - 230 ns read cycles in 16-bit bus mode (see note below) read cycle, sequential address, 16-bit bus mode, t sr16 + t inact - 90 - - ns read cycle, non-sequential address, 16-bit bus mode, t was + t w + t sr16 + t inact - - - 240 ns note: when reading a series of sequential addresses, the read cycle for the frst word (or byte) location is always longer because the HI-6130 asserts the wait output. as long as sequential addresses are then read, automatic prefetch speeds up read access for following words (or bytes) since these occur without wait assertion. HI-6130, hi-6131
holt integrated circuits 276 host write in dual-byte mode (8-bit bus width) showing 2 bytes written for a single 16-bit word using btyp e=1( ?intels tyle ?- output enable and w rite enable) oe we t wr t inact we cs a0 lb a15:1 address oe we or assertion for the next read or wr it e oe d7:0 wa it byte 0 byte 1 t wr t inact host write in word mode (16-bit bus width) showing a one-word write cycle. successive writes to sequential addresses have same timing. using btyp e=1( ?intels tyle ?- output enable and w rite enable) oe we all timing intervals equal 0 ns min unless otherwise indicated. all timing intervals equal 0 ns min unless otherwise indicated. we oe cs a15:1 address oe we or assertion for the next read or wr ite d15:0 word wa it t wr t inact figure 30. register and ram write operations for btype = 1 HI-6130, hi-6131
holt integrated circuits 277 d7:0 str r/ w wa it a0 lb a15: 1 byte 0 byte 1 address host write in dual-byte mode (8-bit bus width) using btyp e=0( ?motorolas tyle?- single and r/ direction select ) str w read/w rite strobe str assertion for the next read or wr ite cs t wr t inact t wr t inact host write in word mode (16-bit bus width) d15:0 str cs a15: 1 word address str assertion for the next read or wr ite r/ w using btyp e=0( ?motorolas tyle?- single read/w rite strobe and r/ direction select ) str w wa it t wr t inact showing 2 bytes written for a single 16-bit word all timing intervals equal 0 ns min unless otherwise indicated. showing a one-word write cycle. successive writes to sequential addresses have same timing. all timing intervals equal 0 ns min unless otherwise indicated. figure 31. register and ram write operations for btype = 0 HI-6130, hi-6131
holt integrated circuits 278 t nsr t sr8 after first byte is read, prefetch allows faster access times for successive reads, as long as addresses are sequential . w ait is always asserted during the first read cycle, is never asserted for successive read cycles to sequential adresses. thisa llows default host bus configuration for the hi-6120 chip select to match the timing characteristics of the faster successive cycles, while the slower initial cycl ei s handled onaw ait -controlled exception basis. w ait can be optionally inverted. host read in dual-byte mode (8-bit bus width) oe we cs a0 lb a15:1 address t w t wa s wa it d7:0 byte 0 byte 1 high-z high-z high- z using btype=1( ?intels tyle?- output enable and w rite enable) oe we we oe or assertion for the next w rite or read t inact t inact after first word is read, prefetch allows faster access times for successive reads, as long as addresses are sequential. w ait is always asserted during the first read cycle, is never asserted for successive read cycles to sequential adresses. thisa llows default host bus configuration for the hi-6120 chip select to match the timing characteristics of the faster successive cycles, while the slower initial cycl ei s handled onaw ait -controlled exception basis. w ait can be optionally inverted. host read in word mode (16-bit bus width) oe cs a15:1 address address+1 we showing two successive words read from sequential addresses using btype=1( ?intels tyle?- output enable and w rite enable) oe we we oe or assertion for the next w rite or read wa it d15:0 word word high-z high-z high- z t nsr t w t wa s t sr16 t inact t inact showing 2 bytes read for a single 16-bit word all timing intervals equal 0 ns min unless otherwise indicated. all timing intervals equal 0 ns min unless otherwise indicated. figure 32. register and ram read operations for btype = 1 HI-6130, hi-6131
holt integrated circuits 279 after first byte is read, prefetch allows faster access times for successive reads, as long as read addresses are sequential. w ait is always asserted during the first read cycle, is never asserted for successive read cycles to sequential adresses. thisa llows default host bus configuration for the hi-6120 chip select to match the timing characteristics of the faster successive cycles, while the slower initial cycl ei s handled o naw ait -controlled exception basis. w ait can be optionally inverted. using btyp e=0( ?motorolas tyle?- single and r/ direction select ) str w read/w rite strobe str r/ w cs a0 lb a15:1 address host read in dual-byte mode (8-bit bus width) str assertion for the next read or wr ite wa it d7:0 byte 0 byte 1 high- z high- z high-z t nsr t sr8 t w t wa s t inact t inact after first word is read, prefetch allows faster access times for successive reads, as long as read addresses are sequential. w ait is always asserted during the first read cycle, is never asserted for successive read cycles to sequential adresses. thisa llows default host bus configuration for the hi-6120 chip select to match the timing characteristics of the faster successive cycles, while the slower initial cycl ei s handled o naw ait -controlled exception basis. w ait can be optionally inverted. using btyp e=0( ?motorolas tyle?- single read/w rite strobe and r/ direction select ) str w str cs a15:1 address addres s+1 r/ w host read in word mode (16-bit bus width) str assertion for the next read or wr ite wa it d15: 0 word word high- z high- z high-z t nsr t w t wa s t sr16 t inact t inact showing 2 bytes read for a single 16-bit word all timing intervals equal 0 ns min unless otherwise indicated. all timing intervals equal 0 ns min unless otherwise indicated. showing two successive words read from sequential addresses figure 33. register and ram read operations for btype = 0 HI-6130, hi-6131
holt integrated circuits 280 28. mil-std-1553 bus interface isolatio n t ransformer point ?ad? txinha/b transmitter receiver 1:2.5 55? 55? 35? 2.5:1 55? 55? 35? busa/b busa/b rx data to manchester decoder tx data from manchester encoder isolation t ransformer point ?ad? figure 34. mil-std-1553 direct coupled test circuits rx data to manchester decoder txinha/b transmitter busa/b busa/b 52.5? (.75 zo) 52.5? (.75 zo) 2.5:1 1:2.5 1:1.4 1.4:1 35? (.5 zo) coupling t ransformer coupling t ransformer isolation t ransformer isolation t ransformer receiver 52.5? (.75 zo) 52.5? (.75 zo) 35? (.5 zo) tx data from manchester encoder point ?at? point ?at? figure 35. mil-std-1553 transformer coupled test circuits HI-6130, hi-6131
holt integrated circuits 281 29. thermal characteristics part number package style condition ja ( o c/w) junction temp, t j ( o c) t a = 25 o c t a = 85 o c t a = 125 o c HI-6130pqx 100-pin pqfp mounted on circuit board 52.7 56 116 156 hi-6131pqx 64-pin pqfp mounted on circuit board 47.75 53 113 153 hi-6131pcx 64-pin qfn heat sink pad unsoldered 31.1 41 101 141 heat sink pad soldered 22.8 37 97 137 30. additional pin / package configurations notes: 1. all vcc, vccp and gnd pins must be connected. 2. see page 1 for HI-6130, 100-pin pqfp package confguration. 30.1. hi-6131pcx (64-pin qfn) top view 64 - ecs - 25 mode - 4 si - 5 sck - 6 so - 7 ce - 3 mr - 14 hi-6131pcx ramedc - 2 bctrig - 1 mclk - 9 gnd - 10 rt1a_0 - 11 rt1a_1 - 12 rt1a_2 - 13 rt1a_3 - 15 rt1a_4 - 16 vcc - 8 rt1ena - 17 rt2a_4 - 32 rt2ap - 31 rt1ap - 18 miso - 19 mosi - 20 vcc - 21 gnd - 22 eecopy - 26 ttclk - 23 mttclk - 24 esck - 27 mtrun - 28 rt2ssf - 29 rt2lock - 30 48 - bendi 47 - test 46 - rt1lock 45 - mtstoff 44 - bcena 43 - busa 39 - vccp 42 - vccp 38 - busb 37 - rt2ena 36 - rt2a_0 35 - rt2a_1 34 - rt2a_2 33 - rt2a_3 40 - busb 41 - busa 50 - vcc 49 - gnd 63 - txinhb 62 - txinha 61 - autoen 60 - vcc 59 - gnd 58 - rt1ssf 57 - active 56 - ready 55 - mtpkrdy 52 - ackirq 51 - irq 54 - rt2mc8 53 - rt1mc8 HI-6130, hi-6131
holt integrated circuits 282 30.2. hi-6131pqx (64-pin pqfp) hi-6131pqx bctrig - 1 ramedc - 2 mode - 4 si - 5 sck - 6 so - 7 vcc - 8 mclk - 9 gnd - 10 rt1a_0 - 11 rt1a_1 - 12 rt1a_2 - 13 rt1a_4 - 16 rt1a_3 - 15 48 - bendi 47 - test 46 - rt1lock 45 - mtstoff 44 - bcena 43 - busa 42 - vccp 39 - vccp 38 - busb 37 - rt2ena 36 - rt2a_0 35 - rt2a_1 34 - rt2a_2 33 - rt2a_3 64 - 63 - txinhb 62 - txinha 61 - autoen 60 - vcc 59 - gnd 58 - rt1ssf 57 - active 56 - ready 55 - mtpkrdy 52 - ackirq 50 - vcc 49 - gnd 54 - rt2mc8 53 - rt1mc8 51 - irq rt1ena - 17 rt1ap - 18 miso - 19 mosi - 20 vcc - 21 gnd - 22 ttclk - 23 mttclk - 24 ecs - 25 eecopy - 26 esck - 27 mtrun - 28 rt2ssf - 29 rt2lock - 30 rt2ap - 31 rt2a_4 - 32 41 - busa 40 - busb mr - 14 ce - 3 HI-6130, hi-6131
holt integrated circuits 283 30.3. hi-6132cxx (121bga, 121lga or 121pga) mtpkt rdy 1 3 2 4 6 5 8 7 9 11 10 1 3 2 4 6 5 8 7 9 11 10 a b c d e f g h j k l a b c d e f g h j k l ram edc data 14 data 11 data 9 data 4 rt1 ssf rt1 mc8 b type nirq bendi ac- tive nce data 12 data 10 auto en data 6 vdd ack irq wpol data 2 dnc ready mode bc trig data 13 tx inha data 7 data 5 test data 1 data 0 dnc rt2 mc8 miso data 15 mosi tx inhb data 8 data 3 mtst off gnd rt1 lock dnc gnd nwait sclk nre vdd gnd vdd vdd bus a bc ena bus a vdd nwe bus nspi mclk gnd vdd gnd gnd nbus b vdd nbus a gnd rt1 a2 rt1 a0 rt1 a1 vdd gnd vdd vdd bus b rt2 ena nbus b mt run addr 0 rt1 ena addr 2 e mosi gnd ee copy rt2 a2 addr 14 rt2 a3 dnc esck addr 1 addr 3 addr 4 addr 6 tt clk vdd rt2 ssf addr 15 addr 13 dnc addr 11 addr 5 rt1 ap e miso addr 7 mtt clk addr 9 rt2 ap addr 12 rt2 a4 bwid rt2 lock nmr rt1 a3 rt1 a4 addr 8 necs addr 10 rt2 a0 gnd rt2 a1 bus b top view notes: a. dnc: do not connect. b. all connections denoted vdd must be connected to 3.3v dc power. c. all 10 connections denoted gnd must be connected to circuit ground. d. bus/nspi (f10) selects 16-bit wide parallel bus or spi operation (see section 6.5. selection of host interface (hi-6132 only) on page 24 ). e. nce: the chip enable signal is shared between 16-bit parallel and spi host interfaces (spi slave select ). f. one column #1 pad (nbusa) and three column #2 pads (busa, busb, nbusb) connect to the external transformers. these conduct high current when the device is transmitting. the three column #2 bus pins may connect through designated column #1 pads to achieve conductor width having suffcient current handling capacity. since nbusa is an outside pad, just a single pad is needed. HI-6130, hi-6131
holt integrated circuits 284 31. ordering information part number lead finish f 100% matte tin (pb-free, rohs compliant) part number temperature range flow burn in i -40 o c to +85 o c i no t -55 o c to +125 o c t no m -55 o c to +125 o c m yes part number package description pq 100 pin plastic quad flat pack, pqfp (100pqs) hi - 6130 pq x f part number lead finish blank tin / lead (sn / pb) solder f 100% matte tin (pb-free, rohs compliant) part number temperature range flow burn in i -40 o c to +85 o c i no t -55 o c to +125 o c t no m -55 o c to +125 o c m yes part number package description pc 64 pin plastic chip-scale package, 9 x 9mm qfn (64pcs) pq 64 pin plastic quad flat pack, pqfp (64pqts) hi - 6131 px x x HI-6130, hi-6131
holt integrated circuits 285 part number temperature range flow burn in i -40 o c to +85 o c i no t -55 o c to +125 o c t no part number package description cg 121 land grid array - lga (121lga) (pb-free, rohs compliant) cp 121 pin grid array - pga (121pga) (pb-free, rohs compliant) cb 121 ball grid array - bga (121bga), non-collapsing high melt temperature pb90 / sn10 solder balls. cf 121 ball grid array - bga (121bga), non-collapsing polymer-core sn96.5 / ag3.5 solder balls. (pb-free, rohs compliant). hi - 6132 cx x HI-6130, hi-6131
holt integrated circuits 286 32. revision history revision date description of change ds6130, rev. new. 8/10/11 initial release rev. a. 9/19/11 corrected numerous typographical errors. updated cross references. corrected imt message filter tables 11 and 12. corrected monitor address list for imt mode, table 13. correct numerous ram address errors. added section on hardware reset and initialization rev. b. 3/14/12 clarifed text descriptions in sections monitor terminal (mt) address list and monitor terminal (mt) data buffers (previously called monitor terminal (mt) stack address table and monitor terminal (mt) command and data stacks respectively. replaced section 9.3 with new sections 9.3. overview of interrupts and 9.4. hardware interrupt behavior . updated section 9.5. interrupt count & log address register (0x000a) . added section 9.6 interrupt log buffer on page 38 . corrected and moved figure 15 to section 9.6 (now figure 3 ). deleted previous section 19.4 interrupt log buffer. updated section 11.15. bus controller interrupt registers and their use . updated section 13.14. smt bus monitor interrupt registers and their use . updated section 16.19. imt bus monitor interrupt registers and their use . updated section 18.14. rt1 and rt2 remote terminal interrupt registers and their use . corrected errors in description of bits 7, 6, and 5 in section 18.1. remote terminal 1 (rt1) confguration register (0x0017) remote terminal 2 (rt2) confguration register (0x0020) . added register diagram. replaced the word stack(s) with buffer(s) throughout the document. clarifed text descriptions in sections standard mode command processing and simplifed mode command processing . corrected reference to mtena input pin throughout the document. should be called mtrun input pin. corrected typographical errors. added hermetically sealed ceramic package option, hi-6132. updated cross references and table of contents. rev. c. 3/25/12 updated table in section 27.5. ac electrical characteristics D HI-6130 host bus interface timing . rev. d. 5/22/12 remove bga package option. add lga and pga options. insert values for tbd in thermal characteristics table. in section 11.6. bus controller (bc) condition code register (read 0x0037) on page 83 , badmsg was incorrectly labelled bit 13 instead of 12. in section 18.1. remote terminal 1 (rt1) confguration register (0x0017) remote terminal 2 (rt2) confguration register (0x0020) on page 144 , corrected text descriptions for bits altbitw and autobsd. clarifed certain descriptions in appendix, section 26 . update pqfp-64 and qfn-64 package dimemsions. HI-6130, hi-6131
holt integrated circuits 287 revision date description of change rev. e. 11/9/12 corrected ordering information for hi-6132 variant. added new section, 23.2. memory test fail address register (0x0024) . added new section, 24. self-test . added self-test registers and memory test fail address register to table 5. register summary . made numerous clarifcations and typo corrections throughout dat asheet. corrected typos on hi-6132cxx pin-out (pins d7, b3, a2). updated ordering information table for hi-6132cxx. rev. f. 12/5/12 corrected pinout of hi-6132cxx package varients (121bga, 121lga and 121pga). corrected other minor typographical errors. HI-6130, hi-6131
holt integrated circuits 288 33. package dimensions detai la see detail a 0 7 .0197 (0.50) bsc .551 (14.0 ) bsc sq .630 (16.0 ) bsc sq .039 (1.0) typ .008 (0.20) rm ax .003 (0.08) rm in .008 (0.20) mi n .009 .002 (.22 .05) .024 .006 (.60 .15) .059 .004 (1.50 .10) .055 .002 (1.40 .05) HI-6130: 100-pin plastic quad flat pack (pqfp) inches (millimeters) package type: 100pqs bsc =? basic spacing between centers ? is theoretical true position dimension and has no tolerance. (jedec standard 95) .354 (9.00) bsc .039 (1.00) max .008 (0.20) typ .0197 (0.50) bsc .010 (0.25) typ .016 .004 (0.40 ) .10 .27 .006 (6.80 ) .15 .27 .006 (6.80 ) .15 bottom view top view .354 (9.00) bsc hi-6131: 64-pin plastic chip-scale package (qfn) heat sink pad on bottom of package. heat sink must be left floating or connected to v dd . do not connect to gnd. inches (millimeters) package type: 64pcs bsc = ?basic spacing between centers? is theoretical true position dimension and has no tolerance. (jedec standard 95) HI-6130, hi-6131
holt integrated circuits 289 hi-6131: 64 pin plastic quad flat pack (pqfp) inches (millimeters) package type: 64pqts .473 (12.00) bsc sq .063 (1.60) .02 (0.50) .009 .002 (0.22 .05) .006 (0.15) .055 .002 (1.40 .05) .004 .002 (0.10 .05) .394 (10.00) see detail a detail a 0 7 bsc sq max .0063 (0.16) bsc r max r min bsc =? basic spacing between centers ? is theoretical true position dimension and has no tolerance. (jedec standard 95) (.6 .15) .024 .006 (1.0) 0.039 bottom view top view a 1 2 3 4 5 6 7 8 9 10 11 b c d e f g h j k l 10 eq. sp. @ .050 (1.27) = 0.5 (12.7) .050 (1.27) 0.045 (1.143) 121x ? = 0.0338 (0.859) inches (millimeters) package type: 121lga hi-6132: 121 land grid array (lga) .075 .008 (1.905 .203) l k j h g f e d c b a .590 (14.986) ceramic package metal cover .590 (14.986) .008 11 10 9 8 7 6 5 4 3 2 1 HI-6130, hi-6131
holt integrated circuits 290 .500 l k j h g f e d c b a 10x .050 1 2 3 4 5 6 7 8 9 10 11 .500 10x .050 121x ?.0338 +0.0020 ?0.0019 ?.012 c a a b m ?.006 c m l k j h g f e d c b a .590 ceramic package metal cover .590 .008 11 10 9 8 7 6 5 4 3 2 1 .075.008 121x .120 121x .011 +.003 ?.001 dimensions in inch hi-6132: pin grid array (121pga) bottom view top view bottom view top view a 1 2 3 4 5 6 7 8 9 10 11 b c d e f g h j k l 10 eq. sp. @ .050 (1.27) = 0.5 (12.7) .050 (1.27) 0.045 (1.143) 121x ? = 0.0338 (0.859) l k j h g f e d c b a .590 (14.986) ceramic package metal cover .590 (14.986) .008 11 10 9 8 7 6 5 4 3 2 1 .075 .008 (1.905 .203) inches (millimeters) package type: 121bga hi-6132: 121 ball grid array (bga) HI-6130, hi-6131

▲Up To Search▲

Price & Availability of HI-6130

	To Download HI-6130 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .